Method and apparatus for producing a test signal for use in a video recorder

• US 4,931,877 A
• Filed: 10/17/1988
• Issued: 06/05/1990
• Est. Priority Date: 11/22/1985
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Stacker, Gunther H., Gebhardt, Arne W., Muller, Horst G.
• Primary Examiner(s): Faber, Alan
• Assistant Examiner(s): Young, W. R.
• Application Number:
  US07/259,456
• Time in Patent Office: 596 Days
• Field of Search: 358/314, 358/335, 358/336, 358/10, 358/139, 358/141, 358/142, 358/257, 360/14.1, 360/14.2, 360/14.3, 360/27, 360/33.1, 360/38.1, 369/47
• US Class Current: 386/263
• CPC Class Codes: H04N 17/06 for recorders
• CPC Class Codes: H04N 5/782 on tape
• CPC Class Codes: H04N 7/0887 for the transmission of programme or channel identifying signals

Abstract

The invention relates to a circuit arrangement for a video recorder, which derives from a video signal the video programming data (VPS data) and generates a test signal that shows whether a television signal is present, whether interference pulses are present, whether VPS data are being transmitted and whether the transmission of the VPS data is free from errors.

Claims

1. A circuit arrangement for controlling the operation of a video recorder from a television signal received thereby, said television signal comprising a digital signal periodically providing program data, a sync signal comprised of a plurality of sync pulses and a first clock signal, said circuit comprising:

(a) means for deriving from said television signal said digital signal, said sync pulses and said first clock signal;

(b) means coupled to said deriving means, for generating a second clock signal synchronized with said first clock signal;

(c) a counter having a first input and a second input, said second input coupled to said deriving means so as to receive therefrom said sync pulses;

(d) a switch having a switch output coupled to said first input of said counter, a first switch input coupled to said generating means so as to receive therefrom said second clock signal and a second switch input coupled to said deriving means so as to receive therefrom said sync pulses, said switch having a first position in which said first switch input is connected to said switch output and a second position in which said second switch input is connected to said switch output, said counter measuring the intervals between said sync pulses when said switch means is in said first position, and counting said sync pulses when said switch means is in said second position;

(e) first monitoring means coupled to said counter and said switch, for monitoring the output of said counter when said switch is in said first position so as to detect the beginning of a first field and for generating in response thereto an identification signal, said identification signal causing said switch to assume said second position;

(f) second monitoring means coupled to said counter and said switch, for monitoring the output of said counter when said switch is in said second position so as to detect the presence of said digital signal and for generating a release signal in response thereto, said release signal causing said switch to assume said first position;

(g) means coupled to said second monitoring means, for separating said program data from said digital signal for the duration of said release signal and for generating a control signal in response thereto;

(h) means coupled to said counter, for providing a detection signal when said switch is in said first position and a pulse occurs in a particular interval between two successive sync pulses or no pulse occurs after a particular interval longer than the line duration of said television signal; and

(i) means coupled to said separating means, said first monitoring means and said detection signal providing means, for generating a test signal which assumes a first state in response to said identification signal or to said detection signal, and which assumes a second state in response to said control signal.

2. A circuit arrangement for a video recorder as claimed in claim 1 further comprising means coupled to said counter for reading the output of said counter into a register contained in said first monitoring means upon each sync pulse input to said counter while said switch means is in said first position and a reset means for resetting said counter thereafter.

3. A circuit arrangement for a video recorder as claimed in claim 1 further comprising a resetting means for resetting said counter to its initial position and said switch from its second to its first position after generation of said release signal.

4. Circuit arrangement as claimed in claim 1, characterized in that said separation means feeds the separated program data to a memory, and that said means for generating a test signal comprises a gating circuit, which when the release signal and the control signal are present, generates a read-out signal that makes the program data available at the output of the memory.

5. Circuit arrangement as claimed in claim 1, characterized in that said means for generating said test signal comprises a gating circuit which after reception of the release signal, changes the test signal briefly to the second state.

6. A circuit arrangement for controlling a video recorder from a television signal received by said recorder, said television signal comprising a plurality of frames each comprising a plurality of pulses and a first field, said first field in turn comprising a data line periodically providing a data signal, said circuit comprising:

(a) first detection means for detecting the beginning of said first field and for providing an identification signal in response thereto;

(b) second detection means coupled to said first detection means, for detecting the beginning of the data line and for providing a release signal in response thereto;

(c) separation means coupled to said second detection means, for separating said data signal from said data line in response to said release signal;

(d) checking means coupled to said separation means, for checking for the presence of said data signal and for lack of errors in said data signal and for providing a control signal in response thereto;

(e) third detection means coupled to a counter, for detecting an interference signal between two successive pulses or the absence of said pulses after a particular time interval longer than the line duration of said television signal and for providing a detection signal in response thereto;

(f) test signal generating means coupled to said checking means, said third detection means and said first detection means, for generating a test signal which assumes a first state in response to said identification signal or said detection signal and which assumes a second state in response to said control signal.

7. A circuit arrangement for a video recorder as claimed in claim 6 further comprising a resetting means for resetting said counter to its initial position and said switch from its second to its first position after generation of said release signal.

8. The circuit of claim 6 further comprising means coupled to said third detection means, for measuring the time interval between each of said pulses and said interference signal if present and wherein said third detection means comprises a register which stores the interval for comparison to a subsequent interval.

9. The circuit arrangement of claim 6 further comprising a switch means having a first position which enables said first detection means and a second position which enables said second detection means, said switch means assuming said first position in response to said release signal.