Programmable tiles

• US 4,931,946 A
• Filed: 03/10/1988
• Issued: 06/05/1990
• Est. Priority Date: 03/10/1988
• Status: Expired due to Term

• Current Assignee: Cirrus Logic International Ltd (Cirrus Logic Incorporated)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Assar, Mahmud M., Patil, Suhas S., Reddy, Dayakar, Ravindra, H., Lin, Ernest S.
• Primary Examiner(s): Chin, Gary
• Assistant Examiner(s): Trans, V. N.
• Application Number:
  US07/166,596
• Time in Patent Office: 817 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 365/94, 365/104, 365/154, 365/190, 307/465, 307/303, 357/42, 357/52
• US Class Current: 257/206
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/1736 in which the wiring can be modified
• CPC Class Codes: H03K 19/17712 one of the matrices at least being reprogrammable

Abstract

Disclosed is a set of functional components (tiles), consisting in part of subgate elements, which, by their design, facilitate the creation of dense integrated circuits, without forfeiting the capability of modifying the functionality of individual tiles by late mask programming techniques. Overall densities approach those obtained with hand-crafted, custom designs can be obtained in part because such components are designed to be tiled throughout a storage logic array, permitting the creation of orthogonal logic gates as well as individual gates (and more complex functions) the functionality of which is distributed horizontally, vertically and even in a zigzag fashion. Moreover, the transition time from prototype to high volume manufacturing is reduced significantly due to the ease with which even complex functions can be repaired and enhanced.

Claims

1. An integrated circuit comprising:

a laterally-extending substrate on which there is defined an elongated function area composed of at least three tile areas joined one to the next, a first and second of the tile areas being structured as terminating tile areas of the elongated function area and a third of the tile areas being differently structured as a middle tile area interposed between the terminating tile areas;

wherein each of the tile areas is of substantially the same size so that a tiled plurality of such tile areas may define a grid;

wherein each tile area includes within its boundaries P and N field effect transistors having source and drain portions defined in a diffusion layer of the substrate and gate portions defined by a gate layer overlying the diffusion layer, the gate portions of the P and N transistors being joined to one another by a common segment of the gate layer;

wherein each tile area further includes an input wire piece extending in a first lateral direction above the gate layer, the input wire piece connecting by way of a contact to a central portion of the common gate layer segment and other portions of the common gate layer segment defining the gate portions of the P and N transistors; and

wherein each tile area also includes an output wire piece extending in a second lateral direction different from the first lateral direction, the output wire piece passing insulatively by the input wire piece of its respective tile area, the output wire piece being positioned to contact to at least the drain portion of one of the P and N transistors in its respective tile area.

2. The integrated circuit of claim 1 wherein each tile area further includes a lame wire for coupling the drain of one of its P and N transistors to the source of a like transistor in another tile area of the elongated function area.

3. The integrated circuit of claim 1 wherein each tile area further includes spaced apart parallel power lines for supplying opposed voltage levels to the source portions of the P and N transistors within that tile area.

4. An integrate circuit comprising:

a laterally extending substrate;

a first elongated function area defined on said substrate to extend in a first lateral direction, the first function area having a first output wire extending therethrough in the first lateral direction and a first input wire extending therein along a second lateral direction at an angle to the first lateral direction, the first function area further having a first set of complementary P and N type field effect transistors, the gates of the transistors in the first set of complementary transistors being coupled to the first input wire, a drain of one transistor in the first set being coupled to the first output wire; and

a second elongated function area defined on said substrate to extend in the second lateral direction, the second function area having a second output wire extending therethrough in the second lateral direction and a second input wire extending therein along the first lateral direction, the second function area further having a second set of complementary P and N type field effect transistors, the gates of the transistors in the second set being coupled to the second input wire, a drain of one transistor in the second set being coupled to the second output wire;

wherein the output wire of the first function area is coextensive with the input wire of the second function area.

5. An integrated circuit comprising:

a laterally-extending upper conductor layer having upper wire pieces;

a laterally-extending lower conductor layer having lower wire pieces, the lower wire pieces crossing under the upper wire pieces;

a via layer interposed between the upper and lower conductor layers, the via layer having defined therein a predetermined pattern of vias for coupling preselected wire pieces of the upper conductor layer to preselected wire pieces of the lower conductor layer;

a base structure composed of one or more laterally-extending base layers below the lower conductor layer, including a conductive gate layer, the base structure including diffusion regions for defining source and drain portions of P-type and N-type field effect transistors, each transistor having a gate electrode defined by a portion of the gate layer;

a first laterally-extending tile area for defining at least part of a first elongated function area, the first tile area encompassing within its boundaries a first portion of the base structure including at least a first P-type transistor and at least a first N-type transistor, wherein the gate electrodes of the first P-type and N-type transistors are defined by a first continuous and nonlinear portion of the gate layer, the first tile area further encompassing a first output wire-piece defined by a wire piece in a first of the lower and upper conductor layers, the first output wire-piece being coupled to a drain portion of at least one of the first P-type and N-type transistors and extending in a first of different lateral directions for conducting a first output signal of the first function are in said first lateral direction, the first tile area further encompassing a first input wire-piece defined by a wire piece in a second of the lower and upper conductor layers, the first input wire-piece extending in a second of the different lateral directions and connecting to the first gate layer portion for conducting a first input signal of the first function area in said second lateral direction to the gate electrodes of the first P-type and N-type transistors; and

a second laterally-extending tile area for defining in combination with the first tile area at least part of the first elongated function area, the second tile area encompassing within its boundaries a second portion of the base structure including at least a second P-type transistor and a second N-type transistor, wherein the gate electrodes of the second P-type and N-type transistors are defined by a second continuous and nonlinear portion of the gate layer, the second tile area further encompassing a second output wire-piece defined by a wire piece in the first of the lower and upper conductor layers, the second output wire-piece extending in the first lateral direction, being coupled to a drain portion of at least one of the second P-type and N-type transistors, and being further coupled to the first output wire-piece of the first tile area for conducting the first output signal of the first function area in said first lateral direction at least partially through the second tile area, the second tile area further encompassing a second input wire-piece defined by a wire piece in the second of the lower and upper conductor layers, the second input wire-piece extending in the second lateral direction and connecting to the second gate layer portion for conducting a second input signal of the first function area in said second lateral direction to the control electrodes of the second P-type and N-type transistors.

6. The integrated circuit of claim 5 wherein the gate layer is composed to polysilicon and at least one of the upper and lower conductor layers is composed of metal.

7. The integrated circuit of claim 5 wherein the first and second gate layer portions each include a substantially U-shaped region.

8. The integrated circuit of claim 5 wherein each tile area has only one P-type transistor and only one N-type transistor.

9. The integrated circuit of claim 5

wherein the first tile area is adjacent to the second tile area;

wherein an output one of the transistors in the first tile area has its drain portion defined by a first output diffusion region, an output one of the transistors in the second tile area has its drain portion defined by a second output diffusion region spaced apart from the first output diffusion region; and

wherein the spaced apart first and second output diffusion regions are electrically connected to one another by the first and second output wire-pieces.

10. The integrated circuit of claim 5 wherein the first and second tile areas have substantially different patternings of wire pieces in their respectively encompassed portions of the upper and lower conductor layers so as to define terminal or middle subfunction portions of the elongated first function area.

11. The integrated circuit of claim 5 further comprising:

one or more series wire-pieces defined within each of the tile areas and coupled to a source or drain portion of one of the P-type and N-type transistors in its respective tile area;

wherein a first series wire-piece in the first tile area is joined to a second series wire-piece in the second tile area so as to couple the source portion of the one transistor in the first tile area to the drain portion of the one transistor in the second tile area.

12. An integrated circuit according to claim 5

wherein the first and second tile areas are adjacent;

wherein an output one of the transistors in the first tile area has its drain portion defined by a first output diffusion region, an output one of the transistors in the second tile area has its drain portion defined by a second output diffusion region spaced apart from the first output diffusion region; and

wherein the spaced apart first and second output diffusion regions are electrically connected to one another by the first and second output wire-pieces.

13. An integrated circuit according to claim 5

wherein each tile area further encompasses a power grid formed of spaced apart Vdd and GND wire-pieces, said Vdd and GND wire-pieces being defined by wire pieces in the second of the lower and upper conductor layers.

14. An integrated circuit according to claim 5

wherein the first and second tile areas are adjacent portions of the first elongated function area and wherein the first and second tile areas have substantially different patternings of wire pieces in their respectively encompassed portions of the upper and lower conductor layers so as to respectively define terminal or middle subfunction portions of the first elongated function area.

15. The integrated circuit of claim 5

wherein the first and second tile areas have respective first and second series wire-pieces each coupled to a source or drain potion of a series-coupled one of the P-type and N-type transistors in its respective tile area and each series wire-piece extends parallel to the output wire-piece of its respective tile area;

and

wherein the first and second series wire-pieces are joined to define a series circuit including the series-coupled one transistor in the first tile area and the series-coupled one transistor in the second tile area.

16. The integrated circuit of claim 15 wherein the first and second tile areas are joined to operatively define a NAND gate which can receive first and second input signals respectively on the first and second input wire-pieces and which can generate a corresponding NAND gate output signal on the first and second output wire-pieces.

17. The integrated circuit of claim 5 wherein each tile area further encompasses part of a power grid formed of spaced apart Vdd and GND wire-pieces arranged in alternating fashion one after the next, said Vdd and GND wire-pieces being defined by wire pieces in the lower or upper conductor layers.

18. The integrated circuit of claim 17 wherein the Vdd and GND wire-pieces are defined in the second of the lower and upper conductor layers to extend in the second lateral direction thereby allowing the output wire-pieces of the first and second tile areas to be extended in the first lateral direction insulatively across the Vdd and GND wire-pieces.

19. The integrated circuit of claim 5 further comprising:

a third laterally-extending tile area for defining at least part of a second elongated function area having a longitudinal axis at an angle to a corresponding longitudinal axis of the first function area, the third tile area encompassing within its boundaries a third portion of the base structure including at least a third P-type transistor and at least a third N-type transistor, wherein the gate electrodes of the third P-type and N-type transistors are defined by a third continuous and nonlinear portion of the gate layer, the third tile area further encompassing a third output wire-piece defined by a wire piece in the second of the lower and upper conductor layers, the third output wire-piece being coupled to a drain portion of at least one of the third P-type and N-type transistors and extending in the second lateral direction for conducting a second output signal belonging to the second function area in said second lateral direction, the third tile area further encompassing a third input wire-piece defined by a wire piece in the first of the lower and upper conductor layers, the third input wire-piece extending in the first lateral direction and connecting to the third gate layer portion for conducting a third input signal belonging to the second function area in said fist lateral direction to the gate electrodes of the third P-type and N-type transistors; and

a fourth laterally-extending tile area for defining in combination with the third tile area at least part of the second function area, the fourth tile area encompassing within its boundaries a fourth portion of the base structure including at least a fourth P-type transistor and a fourth N-type transistor, wherein the gate electrodes of the fourth P-type and N-type transistors are defined by a fourth continuous and nonlinear portion of the gate layer, the fourth tile area further encompassing a fourth output wire-piece defined by a wire piece in the second of the lower and upper conductor layers, the fourth output wire-piece being coupled to a drain portion of at least one of the fourth P-type and N-type transistors and extending in the second lateral direction and being coupled to the third output wire-piece of the third tile area for conducting the second output signal in said second lateral direction at least partially through the fourth tile area, the fourth tile area further encompassing a fourth input wire-piece extending in the first lateral direction and connecting to the fourth gate layer portion for conducting a fourth input signal belonging to the second function area in said first lateral direction to the control electrodes of the fourth P-type and N-type transistors.

20. The integrated circuit of claim 19 wherein an output wire-piece of the first function area is coextensive with an input wire-piece of the second function area.

21. The integrated circuit of claim 19 further comprising:

one or more series wire-pieces defined within each of the tile areas and coupled to a source or drain portion of one of the P-type and N-type transistors in its respective tile area;

wherein a first series wire-piece in the first tile area is joined to a second series wire-piece in the second tile area so as to couple the source portion of the one transistor in the first tile area to the drain portion of the one transistor in the second tile area, and

wherein a third series wire-piece in the third tile area is joined to a fourth series wire-piece in the fourth tile area so as to couple the source portion of the one transistor in the third tile area to the drain portion of the one transistor in the fourth tile area.

22. The integrated circuit of claim 5 wherein the first and second gate layer portions each include a substantially W-shaped region.

23. The integrated circuit of claim 22 wherein the W-shaped region is composed of polysilicon.

24. The integrated circuit of claim 22 wherein the input wire-piece of each tile area is coupled by way of a contact to a substantially middle portion of the W-shaped region.

25. The integrated circuit of claim 22 further comprising one or more free wire-pieces defined within each of the first and second tile areas from wire pieces in the second of the lower and upper conductor layers, the free wire-pieces overlying and being insulated from the W-shaped regions within their respective tile areas such that the free wire-pieces are available for insulatively conducting signals in the second lateral direction through their respective tile areas.