Semiconductor memory having storage buffer to save control data during bulk erase

• US 4,931,997 A
• Filed: 02/23/1988
• Issued: 06/05/1990
• Est. Priority Date: 03/16/1987
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Matsubara, Kiyoshi, Mitsuishi, Naoki, Ozawa, Yoshiyuki, Takamori, Yoh
• Primary Examiner(s): Moffitt, James W.
• Assistant Examiner(s): Ray, Gopal C.
• Application Number:
  US07/159,193
• Time in Patent Office: 833 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 242/198, 365/189.01, 365/195, 365/228, 365/218
• US Class Current: 365/185.04
• CPC Class Codes: G06F 12/1433 for a module or a part of a module
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A volatile storage circuit for latching data is disposed outside a non-volatile memory array. Before a bulk erase of the memory array, some of the data items contained therein are transferred to and held by the storage circuit. The data items thus saved are rewritten to the non-volatile memory array after the bulk erase, or alternatively, on the basis of control data items transferred to the storage circuit, only regions designated by these data items are subjected to the bulk erase. Thus, in case of a bulk erase of an EEPROM, some of the stored data items can be preserved, so as to prevent illicit use of and maintain the integrity of the preserved data. Also the testing time of the data rewritten to the memory array is reduced because of the elimination of the need to test the memory area containing the preserved data in that only the integrity of the memory area containing data sourced externally need be tested.

Claims

1. A non-volatile memory comprising:

a group of non-volatile memory cells having a predetermined memory cell rank containing protective information comprising control data indicative of a select set of the non-volatile memory cells not to be erased during an erasure mode;

a means for electrically writing and erasing data into and from said group of non-volatile memory cells including means for withholding erasure of the select set of non-volatile memory cells not to be erased, while erasing non-indicated memory cells; and

,

volatile storage means for storing the protective information prior to the erasure mode.

2. The non-volatile memory according to claim 1, wherein said volatile storage means further comprises latch means for holding stored data items of a non-volatile memory cell rank at an address designated in a read mode.

3. The non-volatile memory according to claim 1, further comprising rank selection means for selecting a specified rank within said group of non-volatile memory cells operable in a bulk erase mode to form a first signal containing the control data for selecting a predetermined rank to be preserved and subsequently forming a second signal for selecting other ranks.

4. A microcomputer comprising a built-in non-volatile memory comprising a group of non-volatile memory cells, and means for electrically writing and erasing data into and from said group of non-volatile memory cells, whereby as contents of at least one rank of memory cells are conserved, the other memory cell ranks can be erased according to control data retrieved from the group of non-volatile memory cells, the control data represents one rank of the protected memory bells conserved.

5. A non-volatile semiconductor memory comprising:

a memory array comprising a plurality of non-volatile memory cells;

selection means coupled to said memory array for selecting non-volatile memory cells from said memory array during an erasure mode;

information storage means for storing information provided from said selected non-volatile memory cells, said information identifying non-volatile memory cells within said memory array not to be erased during the erasure mode;

erasing means, coupled to said memory array and to said information storage means, for erasing data stored in said non-volatile memory cells while excluding from erasure the non-volatile memory cells identified by said indication information stored in said information storage means.

6. The non-volatile semiconductor memory according to claim 5 wherein said information storage means includes a plurality of latch circuits for storing said information.

7. The non-volatile semiconductor memory according to claim 6 wherein each of said non-volatile memory cells includes an electrically erasable and programmable memory element.

8. In a microcomputer having a random access memory, an interface circuit, a non-volatile memory having a plurality of non-volatile memory cells, and a central processing unit coupled to said random access memory, to said interface circuit and to said non-volatile memory, a method of erasing data stored in said non-volatile memory comprising steps of:

(a) selecting predetermined non-volatile memory cells from the plurality of non-volatile memory cells of said non-volatile memory;

(b) writing information from said predetermined non-volatile memory cells to a storage means, the information indicating non-volatile memory cells not to be erased; and

,

(c) erasing the data stored in said non-volatile memory cells while not erasing the non-volatile memory cells identified by said information stored in said storage means.

9. The method according to claim 8 wherein the erasing comprises electrically erasing the non-volatile memory cells.

10. An integrated circuit card comprising a microcomputer having a random access memory, an interface circuit, a non-volatile memory and a central processing unit coupled to said random access memory, to said interface circuit and to non-volatile memory, wherein said non-volatile memory comprises:

a memory array having a plurality of non-volatile memory cells;

selection means, coupled to said memory array, for selecting non-volatile memory cells from said memory array during an erasure mode;

information storage means for storing information provided from said selected non-volatile memory cells, said information including indication information for identifying non-volatile memory cells within said array not to be erased;

erasing means, coupled to said memory array and to said information storage means, for erasing data stored in said non-volatile memory cells except the non-volatile memory cells identified by said indication information stored to said information storage means.

11. The integrated circuit card according to claim 10, wherein each of said memory cells includes an electrically erasable and programmable memory element.

12. A microcomputer, formed on a single chip, having a random access memory, an interface circuit, a non-volatile memory and a central processing unit coupled to said random access memory, to said interface circuit and to said non-volatile memory, wherein said non-volatile memory comprises:

a memory array having a plurality of non-volatile memory cells;

selection means, coupled to said memory array, for selecting non-volatile memory cells from said memory array during an erasure mode;

information storage means for storing information provided from said selected non-volatile memory cells, said information including indication information for identifying non-volatile memory cells within said memory array not to be erased;

erasing means, coupled to said memory array and to said information storage means, for erasing data stored in said non-volatile memory cells while excluding from erasure the non-volatile memory cells indicated by said indication information stored in said information storage means.

13. The microcomputer according to claim 12 further comprising an external terminal coupled to said non-volatile memory for accessing said non-volatile memory.

14. The microcomputer according to claim 13 further comprising an external control terminal for receiving a control signal and mode setting means, coupled to said external control terminal, for delivering a mode signal to indicate whether said non-volatile memory is accessed by said central processing unit or accessed externally via said external terminal on the basis of said control signal.

15. The microcomputer according to claim 13 wherein said external control terminal includes an external erase control terminal for receiving an erase control signal, and wherein said erasing means includes means responsive to said external erase control signal for erasing data stored in said non-volatile memory cells.

16. The microcomputer according to claim 15 wherein said erasing means includes means, responsive to a control signal from said central processing unit, for erasing data stored in said non-volatile memory cells.

17. The microcomputer according to claim 12 wherein said interface circuit includes communication means for sending data to and receiving data from external equipment, and wherein said microcomputer includes a read only memory for storing a program.

18. The microcomputer according to claim 17 wherein each of said non-volatile memory cells includes an electronically erasable and programmable memory element.