N.sup.+ amorphous silicon thin film transistors for matrix addressed liquid crystal displays

• US 4,933,296 A
• Filed: 08/02/1985
• Issued: 06/12/1990
• Est. Priority Date: 08/02/1985
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Piper, William W., Possin, George E., Parks, Harold G., Castleberry, Donald E.
• Primary Examiner(s): Chaudhuri, Olik
• Application Number:
  US06/761,938
• Time in Patent Office: 1,775 Days
• Field of Search: 148/DIG. 20, 148/DIG. 147, 148/DIG. 53, 357/23.7, 357/71, 156/643, 156/664, 204/192 C, 437/40, 437/43, 437/192, 437/50, 437/181, 437/187
• US Class Current: 438/30
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/103 a-Si
• CPC Class Codes: H01L 21/28512 on semiconductor bodies comprising elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

A thin film FET switching element, particularly useful in liquid crystal displays (LCDs) employs particular materials and is fabricated via a particular process to ensure chemical compatibility and the formation of good electrical contact to an amorphous silicon layer while also producing FETs with desirable electrical properties for LCDs. These materials include the use of titanium as a gate electrode material and the use of N⁺ amorphous silicon as a material to enhance electrical contact between molybdenum source and drain pads and an underlying layer of amorphous silicon. The process of the present invention provides enhanced fabrication yield and device performance.

Claims

1. A process for the fabrication of thin film field effect transistors in active matrix liquid crystal display devices, said process comprising the sequential steps of:

disposing a gate metallization layer pattern on a portion of a first major surface of an insulative substrate, said gate metal comprising titanium, said pattern including gate electrodes and;

disposing a pixel electrode pattern on a portion of the first major surface of said substrate, said pixel electrode material comprising indium tin oxide;

disposing a layer of protective insulative material over said first major substrate surface including said gate metal pattern and said pixel electrode pattern;

disposing a layer of intrinsic amorphous silicon over said protective insulative material;

disposing a layer of N⁺ amorphous silicon over said intrinsic amorphous silicon;

patterning said protective insulative material, said intrinsic amorphous silicon and said N⁺ amorphous silicon layers so as to form islands over said gate metal, whereby each island formed includes protective insulative material, intrinsic amorphous silicon and N⁺ amorphous silicon layers;

disposing a source and drain metallization layer over the first major surface of said substrate; and

patterning said source and drain metallization layer and said N⁺ silicon layer so as to form field effect transistor devices.

2. The fabrication process of claim 1 in which said gate metallization layer pattern is disposed by vapor deposition and plasma etching.

3. The fabrication process of claim 1 in which said pixel electrode pattern is disposed by sputter deposition and wet etching.

4. The fabrication process of claim 1 in which said protective insulating material comprises silicon nitride which is disposed by plasma enhanced chemical vapor deposition.

5. The fabrication process of claim 1 in which said amorphous silicon is disposed by plasma enhanced chemical vapor deposition.

6. The fabrication process of claim 1 in which said N⁺ amorphous silicon layer is disposed by plasma enhanced chemical vapor deposition.

7. The fabrication process of claim 1 in which said source and drain metallization layer is disposed by sputtering.

8. The fabrication process of claim 1 in which said source and drain metallization layer patterning comprises etching in a solution of phosphoric acid, acetic acid and weak nitric acid.

9. The fabrication process of claim 1 further comprising disposing a passivation layer over said substrate.

10. The fabrication process of claim 9 in which said passivation layer comprises silicon nitride which is formed by plasma deposition.

11. The process of claim 1 in which said protective insulative material comprises silicon nitride.

12. The fabrication process of claim 1 in which said source and drain metallization comprises molybdenum.

13. A process for the fabrication of thin film field effect transistors in active matrix liquid crystal display devices, said process comprising the sequential steps of:

disposing a gate metallization pattern on a portion of a first major surface of an insulative substrate, said gate metal comprising titanium, said pattern including gate electrodes and

disposing a pixel electrode pattern on a portion of the first major surface of said substrate, said pixel electrode material comprising indium tin oxide;

disposing a layer of protective insulative material over said first major substrate surface including said gate metal pattern and said pixel electrode pattern;

disposing a layer of intrinsic amorphous silicon over said protective insulative material;

disposing a layer of N⁺ amorphous silicon over said intrinsic amorphous silicon;

disposing a layer of molybdenum over said N⁺ silicon layer;

patterning said molybdenum layer so as to form islands over said gate metal;

patterning said protective insulative material, said intrinsic amorphous silicon and said N⁺ amorphous silicon layers so as to form islands said gate metal, the islands being substantially the same size or slightly larger than said molybdenum island on insulative material layer, the intrinsic amorphous silicon layer, the N⁺ amorphous silicon layer and the molybdenum layer

disposing a source and drain metallization layer over the first major surface of said substrate; and

patterning said source and drain metallization layer and said N⁺ silicon layer so as to form field effect transistor devices.

14. The process of claim 13 in which said protective insulative material comprises silicon nitride.

15. The process of claim 13 in which said source and drain metallization also comprises molybdenum.