Driving circuit for controlling output voltage to be applied to a load in accordance with load resistance

• US 4,933,625 A
• Filed: 01/31/1989
• Issued: 06/12/1990
• Est. Priority Date: 01/31/1988
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Hayakawa, Tatsuo
• Primary Examiner(s): Salce, Patrick R.
• Assistant Examiner(s): STERRETT, JEFFREY L
• Application Number:
  US07/304,728
• Time in Patent Office: 497 Days
• Field of Search: 323/273, 323/274, 323/275, 323/277, 323/280, 323/349, 323/351
• US Class Current: 323/275
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: H03K 17/166 Soft switching

Abstract

The disclosed driving circuit is composed of a driving transistor connectable to a load in accordance with an input signal, a first control device operating in case of driving the load having a relatively large resistance for producing a first control signal effective to control the driving transistor to drive the load by a constant-voltage type operation, a second control device operating in case of driving the load having a relatively small resistance for producing a second control signal effective to control the driving transistor to drive the load by a constant-current type operation, and a selecting device selectively applying either of the first and second control signals to the driving transistor according to the value of the load resistance connected to the driving transistor.

Claims

1. A driving circuit for driving a load having either of large and small resistance, comprising:

driving means connectable to a load for driving the same, said driving means including a driving transistor, a switch controlled by an input signal and a transformer having a primary winding connected to said driving transistor through said switch and a secondary winding connected to said load;

first control means being operative in case of said load having a relatively large resistance for producing a first control signal effective to control said driving means to drive said load by a constant voltage;

second control means being operative in case of said load having a relatively small resistance for producing a second control signal effective to control said driving means to drive said load by a constant current; and

selecting means for selectively applying either of said first and second control signals to said driving means according to the value of load resistance connected to said driving circuit.

2. A driving circuit according to claim 1;

wherein said selecting means includes an adder for adding said first and second control signals to each other to apply the added signals to said driving means.

3. A driving circuit according to claim 1;

wherein said first control means includes a first differential amplifier having an inverting input terminal receptive of a driving voltage applied across said load and a non-inverting input terminal receptive of a first given reference voltage to amplify the difference therebetween to thereby produce said first control signal.

4. A driving circuit according to claim 3;

wherein said first control means includes means for voltage-dividing the voltage at a connection point between said driving transistor and said switch at a given rate to apply the voltage-divided voltage to said inverting input terminal.

5. A driving circuit according to claim 1;

wherein said second control means includes detecting means for detecting a driving current flowing through said load and producing a corresponding detection voltage, and a second differential amplifier having an inverting input terminal receptive of a second given reference voltage and a non-inverting input terminal receptive of said detection voltage to amplify the difference therebetween to thereby produce said second control signal.

6. A driving circuit according to claim 5, wherein said driving transistor has one output terminal connectable to said switch and the other output terminal connected to said detecting means, said detecting means, said driving transistor and said switch being connected in series.

7. A driving circuit according to claim 6;

wherein said driving transistor comprises a MOS transistor having a drain output terminal connected to said detecting means.

8. A driving circuit comprising:

a driving transistor for driving a load in response to an input signal, said load being connected in series to a first side of said driving transistor;

first means for producing a first reference voltage;

a first differential amplifier having a non-inverting input terminal receptive of said first reference voltage produced by said first means and an inverting input terminal receptive of an output voltage obtained from said driving transistor to be applied to said load;

current detecting means connected in series to a second side of said driving transistor opposite to said first side thereof, said current detecting means detecting a current flowing through said driving transistor;

second means for producing a second reference voltage;

a second differential amplifier having an inverting input terminal receptive to said second reference voltage produced by said second means and a non-inverting input terminal receptive of a detected voltage produced by said current detecting means; and

an adder for adding outputs from said first and second differential amplifiers to each other to output the added voltages as a control signal effective to control said driving transistor.

9. A driving circuit according to claim 8;

wherein said load is connected to said driving transistor through a switch the switching operation of which is controlled by said input signal.

10. A driving circuit according to claim 9;

wherein said driving transistor comprises a MOS transistor having a drain terminal connected to said current detecting means and a source terminal connected to said switch.

11. A driving circuit according to claim 9;

further including means for voltage-dividing the voltage at a circuit portion connecting said driving transistor and said switch at a given rate to apply the voltage-divided driving voltage to said inverting input terminal of said first differential amplifier.