Apparatus for maintaining consistency of a cache memory with a primary memory

• US 4,933,835 A
• Filed: 01/19/1989
• Issued: 06/12/1990
• Est. Priority Date: 02/22/1985
• Status: Expired due to Term

• Current Assignee: Intergraph Hardware Technologies Company (Hexagon AB)
• Original Assignee: Intergraph Corporation (Hexagon AB)
• Inventors: Cho, James Y., Sachs, Howard G., Hollingsworth, Walter H.
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US07/300,174
• Time in Patent Office: 509 Days
• Field of Search: 364/200, 364/100
• US Class Current: 711/123
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches

Abstract

A microprocessor system is disclosed having a high speed system bus for coupling system elements, and having a dual bus microprocessor with separate ultra-high speed instruction and data cache-MMU interfaces coupled to independently operable instruction and data cache-MMU, respectively. A main memory is coupled to the system bus for selectively storing and outputting digital information. The instruction and data cache-MMU'"'"'s are coupled to the main memory via the system bus for independently storing and outputting digital information to respective mapped addressable very high speed cache memory. The microprocessor is coupled via separate and independent very high speed instruction and data buses to each of the instruction cache-MMU and data cache-MMU, respectively, for processing data received from the data cache-MMU responsive to instructions received from the instruction cache-MMU. The instruction bus and data bus are exclusive and independent of one another, and allow for simultaneous very high-speed transfer. The data cache-MMU and instruction cache-MMU each have separate dedicated system bus interfaces for coupling to the main memory and to other peripheral devices which are coupled to the system bus. Numerous other system elements can also be coupled to the system bus, including an interrupt controller, an I/O processor, a bus arbiter, an array processor, and other peripheral controller devices.

Claims

1. A computer system comprising:

primary memory means for storing data at storage locations therein;

system bus means, coupled to the primary memory, for communicating data with the primary memory means;

a first data processing element, coupled to the system bus means, for processing data from the primary memory means;

a second data processing element for processing data from the primary memory means;

cache memory means for storing data from the primary memory means, wherein data from the primary memory processed by the first and second data processing elements may be stored in the cache memory; and

cache controller means, coupled to the system bus means, to the second data processing element, and to the cache memory means, for selectively communicating data between the primary memory means and the cache memory means and for communicating data between the cache memory means and the second data processing element, the cache controller means including primary memory access detecting means for detecting when the primary memory means is being accessed by the first data processing element.

2. The computer system according to claim 1 wherein the system bus means further comprises access indicating means for indicating when the primary memory means is being accessed.

3. The computer system according to claim 2 wherein the cache controller means further comprises cache inquiry means, responsive to the access indicating means, for determining whether a storage location being accessed in the primary memory means corresponds to data stored in the cache memory means.

4. The computer system according to claim 3 wherein the primary memory means further comprises access control means for selectively allowing and inhibiting access to the primary memory means when the storage location to be accessed in the primary memory means may correspond to data stored in the cache memory means.

5. The computer system according to claim 4 wherein the cache controller means further comprises inquiry indicating means, coupled to the cache inquiry means and to the system bus means, for providing a first cache inquiry signal to the system bus means when the cache inquiry means is determining whether the primary memory storage location to be accessed corresponds to data stored in the cache memory means.

6. The computer system according to claim 5 wherein the access control means inhibits access to the primary memory means in response to the first cache inquiry signal.

7. The computer system according to claim 6 wherein the inquiry indicating means provides a second cache inquiry signal to the system bus when the cache inquiry means has determined whether the data to be accessed is stored in the cache memory.

8. The computer system according to claim 7 wherein the access control means allows access to the primary memory in response to the second cache inquiry signal.

9. The computer system according to claim 3 wherein the access indicating means further comprises read indicating means for providing a read indicating signal when data is to be retrieved from a selected storage location in the primary memory means.

10. The computer system according to claim 9 wherein, when the selected primary memory storage location corresponds to data stored in the cache memory, the cache controller means couples the cache data corresponding to the selected primary memory storage location to the system bus in response to the read indicating signal.

11. The computer system according to claim 10 wherein the cache controller means couples the cache data to the system bus only when the cache data has been modified since the cache data was stored in the cache memory.

12. The computer system according to claim 10 wherein the cache controller means provides a first ready signal to the system bus means when the cache data is coupled to the system bus.

13. The computer system according to claim 12 wherein the cache controller means further comprises inquiry indicating means, coupled to the cache inquiry means and to the system bus means, for providing a first cache inquiry signal to the system bus means when the cache inquiry means is determining whether the selected primary memory storage location corresponds to data stored in the cache memory means.

14. The computer system according to claim 13 wherein the inquiry indicating means provides a second cache inquiry signal to the system bus when the cache inquiry means has determined whether the selected primary memory storage location corresponds to data stored in the cache memory.

15. The computer system according to claim 14 wherein the primary memory means couples data from the selected storage location to the system bus when the second cache inquiry signal is provided and the first ready signal is absent.

16. The computer system according to claim 15 wherein the primary memory means provides a second ready signal to the system bus when the data from the selected storage location is coupled to the system bus.

17. The computer system according to claim 15 wherein the access indicating means further comprises data type means for indicating whether the selected primary memory storage location corresponds to data which may be stored in the cache memory means.

18. The computer system according to claim 17 wherein the cache inquiry means initiates a cache inquiry when the data type means indicates that the selected primary memory storage location corresponds to data which may be stored in the cache memory means.

19. The computer system according to claim 18 wherein the cache inquiry means does not initiate a cache inquiry when the data type means indicates that the data to be accessed is not store in the cache memory means.

20. The computer system according to claim 19 wherein the second cache inquiry signal is provided when the data type means indicates that the data to be accessed is not stored in the cache memory means.

21. The computer system according to claim 12 wherein the cache controller means includes means for invalidating the data stored in the cache memory which corresponds to the selected primary memory storage location.

22. The computer system according to claim 3 wherein the access indicating means further comprises write indicating means for indicating when data is to be transferred to a selected storage location in the primary memory means.

23. The computer system according to claim 21 wherein the cache controller means includes means for updating the cache memory with the data to be transferred to the selected primary memory storage location when the selected primary memory storage location corresponds to data stored in the cache memory means.