I/O control system using buffer full/empty and zero words signals to control DMA read/write commands

• US 4,933,840 A
• Filed: 12/07/1988
• Issued: 06/12/1990
• Est. Priority Date: 05/21/1985
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Sera, Akihiro, Goukon, Kazuhiko, Shibata, Yuji
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): Mohamed, Ayni
• Application Number:
  US07/281,947
• Time in Patent Office: 552 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/57
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

In an input/output control system: a read/write operation for a control register (REG) under a program mode is achieved by hardware; the system is started or stopped under the control of firmware, and a data transfer in the system is achieved under the control of hardware. Therefore, a high speed data communication is realized, via the system, between a central control unit (CC) and an input/output unit (IO).

Claims

1. An input/output control system connected, via a common bus to a central control unit and, via an external bus to an input/output unit, for controlling transfer of data between the central control unit and the input/output unit, said input/output control system comprising:

a buffer memory, connected to the common bus, for momentarily storing transfer data and for outputting full and empty signals indicating full and empty states thereof;

a control register, connected to the common bus, for storing sets of data transfer control information from the central control unit, the data transfer control information including a number of words to be transferred, and for outputting a zero words signal when the number of words to be transferred is zero;

a microprocessor, connected to the common bus via said control register, for generating commands for initiating and completing data transfer under control of a microprogram;

an input/output unit control circuit, connected to the common and external buses, said buffer memory and said microprocessor, for controlling the input/output unit, only starting and finishing operations of said input/output unit control circuit being controlled by execution of the microprogram in said microprocessor;

direct memory access control means for controlling data transfer using said buffer memory in dependence upon the data transfer control information written in said control register, said direct memory access control means comprising;

an input/output unit direct memory access control circuit connected to said input/output unit control circuit and said buffer memory, for controlling data transfer between said buffer memory and said input/output unit control circuit, using the read and write commands from said microprocessor only for controlling initiation and completion of data transfer; and

a direct memory access control circuit connected to the common bus and said buffer memory, for controlling data transfer between said buffer memory and the common bus using the read and write commands only for controlling initiation and completion of data transfer; and

logic means for generating a first control signal, in dependence upon the full and empty signals, to control generation of the read and write commands by said input/output unit direct memory access control circuit and for generating a second control signal, in dependence upon the full and empty signals and the zero words signal, to control generation of the read and write commands by said direct memory access control circuit, the read and write commands controlling operation of the buffer memory.

2. An input/output control system connected, via a common bus to a central control unit and, via an external bus to an input/output unit, for controlling transfer of data between the central control unit and the input/output unit, said input/output control system comprising:

a buffer memory, connected to the common bus, for momentarily storing transfer data;

a control register, connected to the common bus, for storing sets of data transfer control information from the central control unit;

a microprocessor, connected to the common bus via said control register, for generating commands for initiating and completing data transfer under control of a microprogram;

an input/output unit control circuit, connected to the common and external buses, said buffer memory and said microprocessor, for controlling the input/output unit, only starting and finishing operations of said input/output unit control circuit being controlled by execution of the microprogram in said microprocessor, said input/output unit control circuit issuing an interruption for finish signal to deactivate said microprocessor in response to the data transfer coming to an end

direct memory access control means, connected to the common bus, for controlling data transfer using said buffer memory in dependence upon the data transfer control information written in said control register and, for initiation and completion of data transfer only, the commands from said microprocessor, said direct memory access control means comprising;

an input/output unit direct memory access control circuit connected to said input/output unit control circuit and said buffer memory, for controlling data transfer between said buffer memory and said input/output unit control circuit; and

a direct memory access control circuit connected to the common bus and said buffer memory, for controlling data transfer between said buffer memory and the common bus; and

a program mode control circuit connected between the common bus and said microprocessor, for controlling data transfer under a program mode, said program mode control circuit issuing an interruption for activation signal to activate said microprocessor in response to a data transfer request from the central control circuit.

3. A system as set forth in claim 2, wherein said buffer memory comprises a first in/first-out memory.

4. A system as set forth in claim 3, wherein said first-in/first-out memory comprises:

an input terminal connected to the common bus and said input/output control circuit, for receiving write data;

an output terminal, connected to the common bus and said input/output control circuit, for outputting read data;

a write mode command reception terminal, connected to said direct memory access control circuit and said input/output unit direct memory access control circuit, for receiving write commands;

a read mode command reception terminal, connected to said direct memory access control circuit and said input/output unit direct memory access control circuit, for receiving read commands;

a full terminal, connected to said direct memory access control circuit and said input/output unit direct memory access control circuit, for providing an indication that said first-in/first-out memory is full of the transfer data; and

an empty terminal for providing an indication that said first-in/first-out memory is empty of the transfer data, and

wherein said input/output unit control circuit comprises;

a write mode command reception terminal, connected to said input/output unit direct memory access control circuit, for receiving a write command, said input/output control circuit starting the input/output unit upon receiving the write command in a write mode; and

a read mode command reception terminal, connected to said input/output unit direct memory access control circuit, for receiving a read command, said input/output control circuit starting the input/output unit upon receiving the read command in a read mode.

5. A system as set forth in claim 4,

wherein said input/output unit direct memory access control circuit comprises a control terminal for receiving a first control signal, said input/output unit direct memory access control circuit producing in response to the first control signal a first access signal supplied to one of the write and read mode command reception terminals of said first-in/first-out memory and a second access signal supplied to one of the write and read mode command reception terminals of said input/output unit control circuit, and

wherein said input/output control system further comprises a first logic gate having inputs connected to the full and empty terminals of said first-in/first-out memory and an output, connected to input/output unit direct memory access control circuit, for supplying the first control signal.

6. A system as set forth in claim 5,

wherein said direct memory access control circuit supplies a third access signal to the write and read mode command reception terminals of said first-in/first-out memory in response to a second control signal, and

wherein said input/output control system further comprises a second logic gate having an output connected to said direct memory access control circuit to supply the second control signal and inputs connected to the full and empty terminals of said first-in/first-out memory and to said control register to receive an information signal indicative of a number of transfer words reaching zero, the number of transfer words specified by one of the sets of data transfer control information stored in said control register.

7. A system as set forth in claim 6, wherein said the first-in/first-out memory selectively transfers data from the common bus to the input/output unit in the write mode and from the input/output unit to the common bus in the read mode.

8. A system as set forth in claim 7, wherein the inputs of said first logic gate and said second logic gate are further connected to receive said control register to transfer direction specifying information specifying operation of said input/output unit direct memory access control circuit and said direct memory access control circuit under the write mode and the read mode, selectively, the transfer direction specifying information being stored in one of the sets of data transfer control information in said control register.

9. A system as set forth in claim 8,

further comprising a time supervisor, connected to said second logic gate and the common bus, for detecting a common bus time out representing a condition that no response is returned, after elapse of a predetermined time period, from the central control unit in response to a third control signal, and

wherein said direct memory access control circuit outputs the third control signal on the common bus.

10. A system as set forth in claim 9, wherein the input of said second logic gate are further connected to receive a parity check part indicating whether a parity error exists in the transfer data provided on the common bus (C-BUS).

11. A system as set forth in claim 7, further comprising a selector, connected to the common bus, the input terminal of said first-in/first-out memory, said input/output unit control circuit and said input/output unit direct memory access control circuit, for selecting between the transfer data from the common bus and the transfer data from the input/output unit are for storage in said first-in/first-out memory under the control of said input/output unit direct memory access control circuit.

12. A system as set forth in claim 8,

wherein a main memory is connected to the common bus, and

wherein said direct memory access mode control circuit generates an increment signal to increment main memory address information by one every time the transfer data is supplied via the common bus to the main memory, the main memory address information being stored in one of the sets of data transfer control information in said control register and indicating an address of the main memory where the transfer data is to be written.

13. A system as set forth in claim 4, further comprising a diagnostic check circuit, connected to said first-in/first-out memory, said direct memory access control circuit, and said input/output unit direct memory access control circuit, for selectively executing a diagnostic operation with regard to said first-in/first-out memory, the input/output unit and said microprocessor.

14. A system as set forth in claim 13, wherein said diagnostic check circuit controls said input/output unit direct access control circuit and said direct memory access mode circuit to momentarily stop issuance of write commands and read commands from at least one of said input/output unit direct access control circuit and said direct memory access mode circuit during diagnostic operations.

15. The system as set forth in claim 14, wherein said diagnostic check circuit issues one of a write command and a read command to said first-in/first-out memory under control of the microprogram executed by said microprocessor.

16. The system as set forth in claim 15, wherein said diagnostic check circuit selectively sets up, at least, a first diagnostic mode, a second diagnostic mode and a third diagnostic mode, in which, under the first diagnostic mode, diagnostic check data is communicated only between said microprocessor and said first-in/first-out memory, under the second diagnostic mode, the diagnostic check data is communicated only between said microprocessor, said first-in/first-out memory and the input/output unit, and under the third diagnostic mode, the diagnostic check data is communicated only between said microprocessor, said first-in/first-out memory and the central control unit.

17. A system as set forth in claim 16, wherein said diagnostic check circuit comprises logic gates connected to receive at least for sets of information:

transfer direction specifying information generated by said microprocessor under control of the microprogram, information indicative of activation of said input/output unit direct memory access control circuit, information indicative of activation of said direct memory access control circuit, and status information indicating full and empty status of said first-in/first-out memory, said logic gates outputting first read and write requests to said input/output unit direct memory access control circuit and read and write requests to said direct memory access control circuit.

18. A system as set forth in claim 17, wherein said diagnostic check circuit detects that no problem has occurred in said first-in/first-out memory in the first diagnostic mode, in said first-in/first-out memory and the input/output unit in the second diagnostic mode and in said first-in/first-out memory and said microprocessor in the third diagnostic mode.

19. A system as set forth in claim 16, wherein said diagnostic check circuit is further selectively sets up a fourth mode in which the transfer data in said first-in/first-out memory is processed to form processed transfer data using said microprocessor and the processed transfer data is rewritten in said first-in/first-out memory, the processed transfer data thereafter bring stored in the input/output unit.

20. A system as set forth in claim 19, wherein said microprocessor produces the processed transfer data in the fourth mode by executing a cipher process on the transfer data.

21. A system as set forth in claim 4,

further comprising a first logic gate having a first input connected to the full terminal of said first-in/first-out memory and a second input connected to the empty terminal of said first in/first-out memory and having an output providing a first control signal to said input/output unit direct memory access control circuit, and

wherein said input/output unit direct memory access control circuit, in response to the first control signal from said first logic gate, provides one of a write command to the write mode command reception terminals of said first-in/first-out memory and said input/output unit control circuit and a read command to the read mode command reception terminals of said first-in/first-out memory and said input/output unit control circuit.

22. A system as set forth in claim 21,

wherein the sets of data transfer control information stored in said control register includes a number of words of data to be transferred,

wherein said input/output control system further comprises a second logic gate having a first input connected to the full terminal of said first-in/first-out memory, a second input operatively connected to the empty terminal of said first-in/first-out memory and a third input operatively connected to said control register to receive an information signal indicating that the number of words of data to be transferred is zero and moving an output providing a second control signal to said direct memory access control circuit, and

wherein said direct memory access control circuit, in response to the second control signal from said second logic data, provides one or a write command to the write mode command reception terminal of said first-in/first-out memory and a read command to the read mode command reception terminal of said first-in/first-out memory.

23. A system as set forth in claim 16, wherein said diagnostic check circuit has a fourth mode, the transfer data in said first-in/first-out memory being processed by said diagnostic check circuit in the fourth mode to produce processed transfer data, the processed transfer data being stored in said first-in/first-out memory and thereafter transferred to the input/output unit.