Optimized E.sup.2 pal cell for minimum read disturb

• US 4,935,648 A
• Filed: 06/16/1989
• Issued: 06/19/1990
• Est. Priority Date: 06/15/1988
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Briner, Michael S., Radjy, Nader A.
• Primary Examiner(s): HUDSPETH, DAVID R
• Application Number:
  US07/351,011
• Time in Patent Office: 368 Days
• Field of Search: 365/104, 365/184, 365/185, 307/465, 307/468, 307/469, 307/450, 357/23.5, 364/716
• US Class Current: 365/185.02
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A four device cell is disclosed for an electrically erasable programmable logic device. The four devices include a floating gate tunnel capacitor, a floating gate read transistor having its floating gate and control gate connected respectively to the floating gate and control gate of the tunnel capacitor, a read select transistor for selectively coupling the drain of the floating gate read transistor to a product term output in response to an input term, and a write select transistor for selectively coupling the drain of the floating gate tunnel capacitor to a write data line in response to the signal on a write select line. During sensing, the control gates of all the floating gate tunnel capacitors are kept at a constant voltage V_cg. The drains of all of the floating gate tunnel capacitors are also kept at a constant voltage V_WDL chosen to minimize read disturb on the tunnel capacitor. Preferably V_WDL =V_cg ·V_WDL is applied to the drain of the floating gate tunnel capacitor by applying V_WDL to all the write data lines and applying at least V_WDL +V_T to all the write select lines of the array.

Claims

1. Non-volatile memory apparatus comprising an array (100) of memopry cells (110), each of said cells in said array comprising a floating gate tunnel capacitor (130), said array being organized into N words of M cells each, said array further having an input term for each of said words, a write select line for each of said words, a product term for each corresponding cell in all of said words and a write data line for each corresponding cell in all of said words, said input term for each given one of said words being distinct from said write select line for said given one of said words.

2. Apparatus according to claim 1, wherein said product term for each given one of said corresponding cells in all of said words is distinct from said write data line for said given one of said corresponding cells in all of said words.

3. Apparatus according to claim 2, wherein said floating gate tunnel capacitor in each of said cells in said array comprises a drain (134), a floating gate (138) and a control gate (136), and wherein the control gates in said floating gate tunnel capacitor in all the cells in each particular word are common.

4. Apparatus according to claim 1, wherein each of said cells in said array further comprises:

a floating gate read transistor (140) having a source (142), a drain (144), a floating gate (148) and a control gate (146), said floating gate of said floating gate read transistor in said cell being connected to said floating gate of said tunnel capacitor in said cell and said control gate of said floating gate read transistor in said cell being connected to said control gate of said tunnel capacitor in said cell;

a read select transistor (150) having a source (152), a drain (154) and a select gate (156), said source of said read select transistor in said cell being coupled to said drain of said floating gate read transistor in said cell, said drain of said read select transistor in said cell being coupled to the product term for said cell and said select gate of said read select transistor in said cell being coupled to the input term for said cell; and

a write select transistor (160) having a drain (162), a source (164) and a select gate (166), said source of said write select transistor in said cell being coupled to said drain of said tunnel capacitor in said cell, said drain of said write select transistor in said cell being coupled to the write data line for said cell and said select gate of said write select transistor in said cell being coupled to the write select line for said cell.

5. Apparatus according claim 4, further comprising control circuitry (102) having:

a read word output corresponding to and coupled to each of said input terms in said array;

a write word output corresponding to and coupled to each of said write select lines in said array;

a write data output corresponding to and coupled to each of said write data lines in said array; and

a control gate output corresponding to each given one of said words and coupled to the control gates of the floating gate tunnel capacitor of all the cells in such given one of said words,

said control circuitry having at least a sense mode and a write mode, said control circuitry when operating in said write mode providing write select signals at said write word output and providing writing potential differences across desired ones of said control gate outputs and said write data outputs, and said control circuitry when operating in said sense mode providing said read select signals at said read word outputs, said control circuitry when operating in said sense mode further providing a potential at all of said write word outputs sufficient such that the potential of the drain of the tunnel capacitor in each given cell in said array is substantially equal to the potential of the drain of the write select transistor of said given cell, and said control circuitry when operating in said sense mode further providing a read potential at all of said control gate outputs and the same read potential at all of said write data outputs.

6. Apparatus according to claim 5, wherein said control circuitry further comprises a conductor connecting together all of said control gate outputs.

7. Apparatus according to claim 5, said array being a programmable AND array in which said read word outputs of said control circuitry constitute inputs to said AND array, said product terms constitute product term outputs of said AND array the pattern of programmed data in said cells in said AND array indicate which of said inputs will be wire-ANDed together to form each of said product terms, said apparatus further comprising logical OR means for providing a signal indicative of the logical OR of a particular subset of set product terms.

8. Non-volatile memory apparatus comprising an array (100) of memory cells (110), said array being organized into N words of M cells each, said array further having an input term for each of said words, a write select line for each of said words, a product term for each corresponding cell in all of said words and write data line for each corresponding cell in all of said words, said input term for each given one of said words being distinct from said write select line for said given one of said words, each of said cells in said array comprising:

a floating gate tunnel capacitor (130) having a drain (134), a floating gate (138), and a control gate (136);

a floating gate read transistor (140) having a source (142), a drain (144), a floating gate (148) and a control gate (146), said floating gate of said floating gate read transistor in said cell being connected to said floating gate of said tunnel capacitor in said cell and said control gate of said floating gate read transistor in said cell being connected to said control gate of said tunnel capacitor in said cell;

a read select transistor (150) having a source (152), a drain (154) and a select gate (156). said source of said read select transistor in said cell being connected to said drain of said floating gate read transistor in said cell, said drain of said read select transistor in said cell being connected to the product term for said cell and said select gate of said read select transistor in said cell being connected to the input for said cell; and

a write select transistor (160) having a drain (162), a source (164) and a select gate (166), said source of said write select transistor in said cell being connected to said drain of said tunnel capacitor in said cell, said drain of said write select transistor in said cell being connected to the write data line for said cell and said select gate of said write select transistor in said cell being connected to the write select line for said cell,

said apparatus further comprising control circuitry (102) having;

a read word output corresponding to and coupled to each of said input terms in said array;

a write word output corresponding to and coupled to each of said write select lines in said array;

a write data output corresponding to and coupled to each of said write data lines in said array; and

a control gate output coupled to the coupled to the control gates of the floating gate tunnel capacitor of all the cells in said array,

said control circuitry having at least a cell charge mode, a cell discharge mode and a sense mode,

said control circuitry when operating in said cell charge mode providing write select signals on at least selected ones of said write word outputs, providing a high voltage at said control gate output and providing substantially ground potential on at least selected ones of said write data outputs,

said control circuitry when operating in said cell discharge mode providing write select signals on at least selected ones of said write word outputs, providing substantially ground potential at said control gate output and providing a high voltage on at least selected ones of said write data outputs, and

said control circuitry when operating in said sense mode providing said read select signals at said read word outputs, providing a read potential V_cg at said control gate output, providing said read potential V_cg at all of said data outputs, and providing at all of said write word outputs a potential at least as high as said read potential V_cg plus the V_T of one of said write select transistors.