Method and apparatus for testing missile systems
First Claim
1. An apparatus for testing missile systems, said apparatus electrically communicating with a computer and with a data processor of a missile, said processor of said missile having a plurality of memory buses, said computer for providing control signals to and for receiving data from said apparatus, said apparatus comprising:
- means for decoding said control signals to determine data to be collected in real-time;
data processor interface buffer means for interfacing said apparatus with said data processor to provide control signals to said data processor and to receive information appearing on at least one of said memory buses, said data processor causing information to appear on at least one of said memory buses in response to said control signals; and
means for real-time collection of data appearing on at least one of said memory buses, said means for real-time collection of data for receiving data from said at least one memory bus through said interface buffer means and for providing collected data to said computer for test and evaluation.
3 Assignments
0 Petitions
Accused Products
Abstract
A method and apparatus for testing missile software is disclosed. The appartus (10) comprises a missile data processor interface circuit (14) for interfacing the data processor (16) of the missile with the apparatus (10). The apparatus (10) further comprises a circuit (18) for real-time collection of information appearing on at least one of the memory buses of the missile data processor. The circuit (18) for real-time collection of data is in electrical communication with the data processor interface circuit (14) and a computer (24).
-
Citations
42 Claims
-
1. An apparatus for testing missile systems, said apparatus electrically communicating with a computer and with a data processor of a missile, said processor of said missile having a plurality of memory buses, said computer for providing control signals to and for receiving data from said apparatus, said apparatus comprising:
-
means for decoding said control signals to determine data to be collected in real-time; data processor interface buffer means for interfacing said apparatus with said data processor to provide control signals to said data processor and to receive information appearing on at least one of said memory buses, said data processor causing information to appear on at least one of said memory buses in response to said control signals; and means for real-time collection of data appearing on at least one of said memory buses, said means for real-time collection of data for receiving data from said at least one memory bus through said interface buffer means and for providing collected data to said computer for test and evaluation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
-
-
17. An apparatus for testing missile systems, said apparatus electrically communicating with the operand memory and the program memory of a missile data processor through a plurality of memory buses, said apparatus further electrically communicating with a computer, said apparatus comprising:
-
a data processor interface buffer electrically communicating with said operand memory and said program memory; an external random access memory electrically communicating with said program memory; a logical interface unit for collecting data from said operand memory and said program memory in real-time, said logical interface unit electrically communicating with said data processor interface buffer; a data processor simulator operable to simulate the output of said data processor, said data processor simulator electrically communicating with said logical interface unit and said external random access memory; and a computer interface module operable to interface said logical interface unit and said external random access memory with said computer. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
-
-
33. A method for testing missile systems, said missile having a data processor electrically communicating with a memory through a plurality of memory buses said method comprising the steps of:
-
providing a computer to control collection of data appearing on said memory buses in real-time; receiving and decoding control signals from said computer to determine information to be collected in real-time from said memory buses; providing control signals to said processor through an interface buffer to cause data to appear on at least one of said memory buses; receiving information appearing on at least one of said memory buses through said data processor interface buffer; collecting in real-time the information appearing on at least one of said memory buses through said data processor interface buffer; and delivering said information collected in real-time to said computer. - View Dependent Claims (34, 35, 36, 37, 38, 39)
-
-
40. A system for testing a missile, said missile of the type having a data processor with a plurality of memory buses, said test system comprising;
-
a computer for providing control signals to determine data to be collected from said data processor; a decoder for decoding said control signals; a data processor interface buffer means for providing control information to said data processor to cause data to appear on at least one of said memory buses; and means in communication with said computer and said interface buffer for real-time collection of data appearing on said at least one memory bus, said means for real-time collection of data for receiving data appearing on said memory buses through said interface buffer means, and for providing collected information to said computer. - View Dependent Claims (41, 42)
-
Specification