Method and apparatus for testing missile systems

• US 4,935,881 A
• Filed: 04/14/1987
• Issued: 06/19/1990
• Est. Priority Date: 04/14/1987
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Lowenson, Jeffrey, Hessamian, Khosrow
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Ramirez, Ellis B.
• Application Number:
  US07/038,253
• Time in Patent Office: 1,162 Days
• Field of Search: 364/550, 364/423, 364/602, 364/900, 364/551.01, 364/578, 364/579, 364/580, 364/443, 340/945, 369/21, 360/5, 73/769, 73/583, 73/560
• US Class Current: 702/122
• CPC Class Codes: F41G 7/006 Guided missiles training or simulation devices
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/2273 Test methods
• CPC Class Codes: G06F 11/364 tracing values on a bus

Abstract

A method and apparatus for testing missile software is disclosed. The appartus (10) comprises a missile data processor interface circuit (14) for interfacing the data processor (16) of the missile with the apparatus (10). The apparatus (10) further comprises a circuit (18) for real-time collection of information appearing on at least one of the memory buses of the missile data processor. The circuit (18) for real-time collection of data is in electrical communication with the data processor interface circuit (14) and a computer (24).

Claims

1. An apparatus for testing missile systems, said apparatus electrically communicating with a computer and with a data processor of a missile, said processor of said missile having a plurality of memory buses, said computer for providing control signals to and for receiving data from said apparatus, said apparatus comprising:

means for decoding said control signals to determine data to be collected in real-time;

data processor interface buffer means for interfacing said apparatus with said data processor to provide control signals to said data processor and to receive information appearing on at least one of said memory buses, said data processor causing information to appear on at least one of said memory buses in response to said control signals; and

means for real-time collection of data appearing on at least one of said memory buses, said means for real-time collection of data for receiving data from said at least one memory bus through said interface buffer means and for providing collected data to said computer for test and evaluation.

2. The apparatus in claim 1, wherein said means for real-time collection of data is operable to cause said computer to pause when the information appearing on at least one of said memory buses is of a predetermined value.

3. The apparatus of claim 1, wherein said means for real-time collection of data is operable to count the number of occurrences that information appearing on at least one of said memory buses is of a particular value.

4. The apparatus of claim 1, wherein said means for real-time collection of data is operable to latch information appearing on at least one of said memory buses.

5. The apparatus of claim 1, wherein said means for real-time collection of data is operable to trace information appearing on at least one of said memory buses.

6. The apparatus of claim 1, wherein said means for real-time collection of data comprises a XRAM in electrical communication with said data processor interface buffer means.

7. The apparatus of claim 1, wherein said means for real-time collection of data comprises a data processor simulator, said data processor simulator operable to simulate the output of said data processor.

8. The apparatus of claim 7, wherein said means for real-time collection of data further comprises a logical interface unit operable to permit selective collection of data from said data processor and said data processor simulator.

9. The apparatus of claim 8, wherein said means for real-time collection of data further comprises a computer interface module operable to interface said logical interface unit and said external random access memory with said computer.

10. The apparatus of claim 1, wherein said means for real-time collection of data comprises a logical interface unit.

11. The apparatus of claim 10, wherein said logical interface unit comprises a random access memory electrically communicating with said data processor interface buffer means, said random access memory operable to store information appearing on one of said memory buses when said data processor executes a write command.

12. The apparatus of claim 11, wherein said logical interface unit further comprises a first FIFO memory, said first FIFO memory being selectively operable to continuously receive information appearing on at least one of said memory buses.

13. The apparatus for claim 12, wherein said first FIFO memory is further selectively operable to receive information appearing on one of said memory buses when the information appearing on one of said buses is of a predetermined value.

14. The apparatus of claim 13, wherein said logical interface unit further comprises a second FIFO memory, said second FIFO memory being selectively operable to continuously receive information appearing on at least one of said memory buses.

15. The apparatus of claim 14, wherein said second FIFO memory is further selectively operable to receive information appearing on one of said memory buses when the information appearing on one of said buses is of a predetermined value.

16. The apparatus of claim 1 wherein said means for real-time collection of data comprises means for a storing a test program.

17. An apparatus for testing missile systems, said apparatus electrically communicating with the operand memory and the program memory of a missile data processor through a plurality of memory buses, said apparatus further electrically communicating with a computer, said apparatus comprising:

a data processor interface buffer electrically communicating with said operand memory and said program memory;

an external random access memory electrically communicating with said program memory;

a logical interface unit for collecting data from said operand memory and said program memory in real-time, said logical interface unit electrically communicating with said data processor interface buffer;

a data processor simulator operable to simulate the output of said data processor, said data processor simulator electrically communicating with said logical interface unit and said external random access memory; and

a computer interface module operable to interface said logical interface unit and said external random access memory with said computer.

18. The apparatus of claim 17, wherein said apparatus permits the contents of said program memory to be dumped onto said external random access memory.

19. The apparatus of claim 17, wherein said logical interface unit is further operable to deliver information to said data processor so that the hardware driven by said data processor may be tested.

20. The apparatus for claim 17, wherein said data processor interface buffer comprises a plurality of translators operable to convert the logic levels associated with said data processor into the logic levels associated with said external random access memory and said logical interface unit.

21. The apparatus of claim 20, further comprising a first multiplexer operable to multiplex information from said data processor and said data processor simulator, said first multiplexer electrically communicating with said logical interface unit and said external random access memory.

22. The apparatus of claim 21, wherein said apparatus further comprises a second multiplexer operable to multiplex information from said data processor and said data processor simulator, said second multiplexer electrically communicating with said logical interface unit.

23. The apparatus in claim 22, wherein said logical interface unit is operable to cause said computer to pause when the information appearing on one of said memory buses is of a predetermined value.

24. The apparatus of claim 23, wherein said logical interface unit is operable to count the number of occurrences that information appearing on one of said memory buses is of a predetermined value.

25. The apparatus of claim 24, wherein said logical interface unit is operable to latch information appearing on one of said memory buses.

26. The apparatus of claim 25, wherein said logical interface unit is operable to trace information appearing on one of said memory buses.

27. The apparatus of claim 26, wherein said logical interface unit comprises a random access memory electrically communicating with said data processor interface buffer, said random access memory operable to store information appearing on one of said memory buses when the data processor executes a write command.

28. The apparatus of claim 27, wherein said logical interface unit further comprises a first FIFO memory, said first FIFO memory being selectively operable to continuously receive information appearing on one of said memory buses.

29. The apparatus for claim 28, wherein said first FIFO memory is further selectively operable to receive information appearing on one of said memory buses when the information appearing on one of said buses is of a predetermined value.

30. The apparatus of claim 29, wherein said apparatus further comprises a second FIFO memory, said second FIFO memory being selectively operable to continuously receive information appearing on one of said memory buses.

31. The apparatus of claim 30, wherein said second FIFO memory is further operable to selectively receive information appearing on one of said memory buses when the information appearing on one of said memory buses is of a predetermined value.

32. The apparatus of claim 31, wherein said external random access memory comprises a XRAM.

33. A method for testing missile systems, said missile having a data processor electrically communicating with a memory through a plurality of memory buses said method comprising the steps of:

providing a computer to control collection of data appearing on said memory buses in real-time;

receiving and decoding control signals from said computer to determine information to be collected in real-time from said memory buses;

providing control signals to said processor through an interface buffer to cause data to appear on at least one of said memory buses;

receiving information appearing on at least one of said memory buses through said data processor interface buffer;

collecting in real-time the information appearing on at least one of said memory buses through said data processor interface buffer; and

delivering said information collected in real-time to said computer.

34. The method of claim 33, wherein said step of collecting in real-time the information appearing on one of said memory buses comprises the step of generating a pause signal when the information appearing on one of said memory buses is of a predetermined value.

35. The method of claim 33, wherein said step of collecting in real-time the information appearing on one of said memory buses comprises the step of generating a signal when the information appearing on one of said memory buses occurs a predetermined number of times.

36. The method of claim 33, wherein said step of collecting in real-time information appearing on one of said memory buses comprises the step of latching information appearing on one of said memory buses when the information appearing on one of said memory buses is of a predetermined value.

37. The method of claim 33, wherein said step of collecting in real-time information appearing on one of said memory buses comprises the step of tracing information appearing on one of said memory buses.

38. The method of claim 33, comprising the additional step of dumping the contents of said memory onto an external random access memory.

39. The method of claim 33, wherein said method comprises the additional step of delivering instructions from a computer to said data processor so that the hardware being driven by said data processor may be tested.

40. A system for testing a missile, said missile of the type having a data processor with a plurality of memory buses, said test system comprising;

a computer for providing control signals to determine data to be collected from said data processor;

a decoder for decoding said control signals;

a data processor interface buffer means for providing control information to said data processor to cause data to appear on at least one of said memory buses; and

means in communication with said computer and said interface buffer for real-time collection of data appearing on said at least one memory bus, said means for real-time collection of data for receiving data appearing on said memory buses through said interface buffer means, and for providing collected information to said computer.

41. The system of claim 40 wherein said means for real time collection of data comprises means for storing a test program.

42. The system of claim 40 wherein said means for real-time collection of data comprises a data processor simulator, said simulator operable to simulate the output of said missile data processor.