Method of making a superlattice heterojunction bipolar device

• US 4,937,204 A
• Filed: 01/04/1989
• Issued: 06/26/1990
• Est. Priority Date: 03/15/1985
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Ishibashi, Akira, Mori, Yoshifumi, Itabashi, Masao
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Bunch, William D.
• Application Number:
  US07/293,333
• Time in Patent Office: 538 Days
• Field of Search: 148/DIG. 56, 148/65, 148/67, 148/72, 148/95, 148/97, 148/110, 148/119, 148/160, 148/169, 156/610-615, 357/3, 357/4, 357/16, 357/17, 357/34, 437/81, 437/105, 437/107, 437/108-112, 437/126, 437/129, 437/133, 437/976
• US Class Current: 117/89
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/7376 Resonant tunnelling transistors
• CPC Class Codes: Y10S 148/011 Bipolar transistors
• CPC Class Codes: Y10S 148/056 Gallium arsenide
• CPC Class Codes: Y10S 148/072 Heterojunctions
• CPC Class Codes: Y10S 148/097 Lattice strain and defects
• CPC Class Codes: Y10S 148/119 Phosphides of gallium or indium
• CPC Class Codes: Y10S 148/16 Superlattice

Abstract

A semiconductor apparatus is disclosed, in which the entire or part of an electron active region is formed by a superlattice structure semiconductor layer in which a plurality of different semiconductor layers, less than 8 monolayers, and containing a fraction or a binary compound semiconductor layers are alternately and epitaxially grown and a main current direction is selected to be in the direction perpendicular to the laminae of said superlattice layers.

Claims

1. A method of forming a superlattice device comprising the successive steps of:

(a) epitaxially growing on a semiinsulating substrate an N type GaAs collector layer of low resistivity;

(b) epitaxially growing an N type, AlGaAs collector layer having a large band-gap;

(c) epitaxially growing a P doped superlattice structure, constituting a base layer and forming a pn junction with the AlGaAs collector layer by forming n monolayers of a first compound semiconductor followed by m monolayers of a second compound semiconductor followed by n monolayers of the first compound semiconductor, and so on, ending with m monolayers of the second semiconductor, where n and m are less than eight;

(d) epitaxially growing an N type AlGaAs emitter layer having a large band-gap and which forms an emitter junction of the heterojunction type with the superlattice base layer;

(e) epitaxially growing an N type GaAs emitter layer;

(f) epitaxially growing an N type GaAs emitter layer of low resistivity; and

(g) causing electrons to flow perpendicularly through the monolayers.

2. A method of forming a superlattice device as recited in claim 1 wherein the step of forming the superlattice structure comprises the successive steps of forming n monolayers of GaAs followed by m monolayers of AIAs followed by n monolayers of GaAs, and so on, ending with m monolayers of AIAs, where n and m are less than eight.

3. A method of forming a superlattice device as recited in claim 1 wherein the step of epitaxially growing the collector layer on the substrate comprises the step of growing it on a Cr doped GaAs substrate.

4. A method of forming a superlattice device as recited in claim 1 wherein the steps of forming the superlattice structure comprise repeating the forming steps until the thickness of the superlattice structure is between 1300 to 2500 Å

thick.

5. A method of forming a superlattice device as recited in claim 1 wherein in the steps of forming the superlattice layer, m=n.