Method and apparatus for estimating fault coverage

• US 4,937,765 A
• Filed: 07/29/1988
• Issued: 06/26/1990
• Est. Priority Date: 07/29/1988
• Status: Expired due to Term

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Shupe, Paul A., Diss, William C., Ausec, Michael E., Berg, William C.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/226,430
• Time in Patent Office: 697 Days
• Field of Search: 364/488-490, 364/570, 364/578, 371/23`25, 324/73 R, 324/73 AT, 324/73 PC
• US Class Current: 702/187
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability
• CPC Class Codes: G01R 31/318392 for sequential circuits G01R31/318544 takes precedence

Abstract

Method and apparatus estimates fault coverage of a set of test vectors to be applied to a circuit containing sequential elements. The apparatus permits sequential elements to be represented as functional blocks rather than combinational circuits with feedback. This is accomplished by taking into account the external state of the sequential element during circuit simulation. The apparatus also takes into account high impedance as possible inputs and outputs.

Claims

1. Apparatus for estimating fault coverage of a set of test vectors applied to a digital circuit which includes in its circuit elements a sequential element and whose circuit description may be measured into a computer for simulation, comprising:

means for defining an output of a sequential element in terms of an input and internal state of the element, the element having an input pin to receive an input and an output pin to provide an output;

means for creating for at least one input pin of the sequential element at least one faulty copy of the element, a copy with the input pin having an input stuck at a logic 1 or a copy having the input stuck at a logic 0, said input being a fault;

means for receiving a set of test vectors to be applied to the digital circuit;

means for simulating the behavior of the digital circuit in response to the test vectors, the simulation including simulating the behavior with the sequential element and with a faulty copy of the element in place thereof;

means for determining from the simulations the outputs of the sequential element and of the faulty copy;

means for comparing the output of the sequential element with the output of a faulty copy to determine which input-output combinations for the sequential element are sensitive to a fault on the input pin, a combination defined as sensitive if the output of the sequential element and a faulty copy differ after taking into account the input and the internal state if the sequential element; and

means for estimating, based on the determined sensitivities, a percentage of faults in the digital circuit covered by the set of test vectors.

2. The apparatus of claim 1 in which the means for determining the outputs of the sequential element and the faulty copy includes means for distinquishing between outputs of logic 1, logic 0 and a high impedance state.

3. The apparatus of claim 1 in which the estimating means includes:

sampling means for sampling the simulation of the digital circuit over a number of time frames, the sampling means storing a count of the number of time frames in which an input pin of the sequential element has an input of a logic 1 and a count of the number of time frames the input pin has a logic 0, and further storing the number of time frames in which each input-output combination is sensitive; and

analyzing means for;

calculating from the counts and sensitivities stored by the sampling means how often an input on an input pin can be observed at a primary output of the digital circuit, said input being observed if a change in the input at the input pin causes a change in the input at the primary output,

calculating from the observabilities and the counts stored by the sampling means a probability of detection of a fault at each input pin of each circuit element in the digital circuit,

calculating an arithmetic means of the detection probabilities, and

providing a fault coverage percentage by dividing the number of faults with detection probabilities above the arithmetic means by the total number of potential faults in the digital circuit.

4. The apparatus of claim 3 wherein the analyzing means includes means for listing as an undetected fault any fault with a detection probability below the arithmetic mean.

5. The apparatus of claim 1 including means for limiting the number of faulty copies simulated, said means simulating a copy only if the copy has a fault at an input pin with a logic value different from that applied to the corresponding input pin of the sequential element.

6. The apparatus of claim 1 including means for removing from the computer, after simulation, a faulty copy having an internal state and output identical to the internal state and output of the sequential element.

7. A method of estimating fault coverage of a set of test vectors applied to a digital circuit which includes in its circuit elements a sequential element and whose circuit description may be entered into a computer for simulation, comprising:

defining an output of a sequential element in terms of an input and internal state of the element, the element having an input pin to receive an input and an output pin to provide an output;

creating for at least one input pin of the sequential element at least one faulty copy of the element, a copy with the input pin having a input stuck at a logic 1 or a copy having the input stuck at a logic 0, said input being a fault;

receiving a set of test vectors to be applied to the digital circuit;

simulating the behavior of the digital circuit in response to the test vectors, the simulation including simulating the behavior with the sequential element and with the faulty copy of the element in place thereof;

determining from the simulations the output of the sequential element and the faulty copy;

comparing the output of the sequential element with the output of a faulty copy to determine which input-output combinations for the sequential element are sensitive to a fault on the input pin, a combination defined as sensitive if the output of the sequential element and a faulty copy differ after taking into account the input and the internal state of the sequential element; and

estimating, based on the determined sensitivities, a percentage of faults in the digital circuit covered by the set of test vectors.

8. The method of claim 7 in which determining the outputs of the sequential element and the faulty copy includes distinquishing between outputs of logic 1, logic 0 and a high impedance state.

9. The method of claim 7 in which estimating the percentage of faults based on the determined sensitivities comprises:

sampling the simulation of the digital circuit over a number of time frames;

storing a count of the number of time frames in which an input pin of the sequential element has an input of a logic 1 and a count of the number of time frames the input pin has a logic 0;

storing the number of time frames in which each input-output combination is sensitive;

calculating from the stored counts and sensitivities how often an input on an input pin can be observed at a primary output of the digital circuit, said input being observed if a change in the input at the input pin causes a change in the output at the primary output;

calculating from the observabilities and the stored count a probability of detection of a fault at each input pin of each circuit element in the digital circuit;

calculating an arithmetic means of the detection probabilities; and

calculating a fault coverage percentage by dividing the number of faults with detection probabilities above the means by the total number of potential faults in the digital circuit.

10. The method of claim 9 including listing as an undetected fault any fault with a detection probability below the arithmetic mean.

11. The method of claim 7 including limiting the number of faulty copies required for simulation by simulating a copy only if the copy has a fault at an input pin with a logic value different from that applied to the corresponding input pin of the sequential element.

12. The method of claim 7 including removing from the computer, after simulation, a faulty copy having an internal state and output identical to the internal state and output of the sequential element.

13. The method of claim 7 wherein estimating the percentage of faults covered is followed by entering additional test vectors to be applied to the digital circuit.

14. A method of determining which input-output combinations for a sequential element in a digital circuit are sensitive to a fault on an input pin of the sequential element, comprising:

defining an output of the sequential element in terms of an input and internal state of the element, the element having an input pin to receive an input and an output pin to provide an output;

creating for at least one input pin of the sequential element at least one faulty copy of the element, a copy with the input pin having an input stuck at a logic 1 or a copy having the input stuck at a logic 0, said input being a fault;

simulating the behavior of the sequential element in response to an input applied to the input pin, the simulation including simulating the behavior with the sequential element and with the faulty copy of the element in place thereof;

determining from the simulation the outputs of the sequential element and the faulty copy; and

comparing the output of the sequential element with the output of a faulty copy to determine which input-output combinations for the sequential element are sensitive to a fault on the input pin, a combination defined as sensitive if the output of the sequential element and a faulty copy differ after taking into account the input and the internal state of the sequential element.