High performance dynamic ram interface

• US 4,937,791 A
• Filed: 06/02/1988
• Issued: 06/26/1990
• Est. Priority Date: 06/02/1988
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Athas, William C. Jr., Steele, Craig S., Seitz, Charles L.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Ray, Gopal C.
• Application Number:
  US07/201,430
• Time in Patent Office: 754 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 365/235, 365/230
• US Class Current: 365/230.03
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

A method and associated apparatus for accessing a plurality of DRAMs in the static column mode by a high performance instruction processor to provide minimum wait state accessing thereby. The method comprises the steps of, having the instruction processor emit each instruction address as an address containing a bank number field, a row address field, and column address field; providing a table for storing a set of open pages being the current row address for each bank where a bank is associated with a respective one of the plurality DRAMs; for each instruction address emitted from the instruction processor, determining whether there is a match between the row address stored in the table and the row address emitted from the instruction processor employing the bank number as an index into the table of open pages; if the two addresses match, continuing the memory access to the indicated bank in a continuing static column mode; and, if the two addresses do not match, overwriting the old address for the indicated bank in the table with the new row address and continuing the memory access by beginning a new static column mode access to the indicated bank. In the preferred embodiment, the method includes, as necessary, aborting the access in progress if the two addresses do not match prior to beginning the new static column mode access to the indicated bank and advising the instruction processor that the access in progress is being aborted and being begun again.

Claims

1. A DRAM memory subsystem capable of minimum wait state accessing by a high performance device accessing outputting a series of row and column addresses for data to be accessed comprising:

(a) a DRAM comprised of rows and columns and operable in a static column mode in response to address requests asserted at RAS and CAS inputs thereof; and

,

(b) access optimization logic means operably connected for receiving a first row and column address as output by the device, for asserting said first row and column address at said RAS and CAS inputs, for receiving a second row and column address as output by the device, for changing the column address being asserted at said CAS input to correspond to said second column address, for checking said second row address against said first row address, and for reasserting said second row and column address at said RAS and CAS inputs if said second row address is not the same as said first row address.

2. The DRAM memory subsystem of claim 1 wherein:

said access optimization logic means includes means for aborting an access to said DRAM prior to reasserting said second row and column address at said RAS and CAS inputs if said second row address is not the same as said first row address.

3. The DRAM memory subsystem of claim 1 wherein there are a plurality of said DRAMs each identifiable by a bank number and the device includes a bank address as part of each row and column address for data to be accessed and additionally comprising:

(a) memory table means for storing the presently being asserted row address for each bank; and

wherein,

(b) said access optimization logic means includes means for storing the presently being asserted row address for each bank in said memory table means, for changing the column address being asserted at said CAS input on said DRAM indicated by the bank address portion of second address from the device to correspond to said second column address, and for checking said second row address against said first row address as stored in said memory table means for the bank indicated by the bank address portion of second address from the device.

4. The method of operating a DRAM memory subsystem having a DRAM comprised of rows and columns and operable in a static column mode in response to address requests asserted at RAS and CAS inputs thereof to provide minimum wait state accessing by a high performance memory accessing device outputting a series of row and column addresses for data to be accessed comprising the steps of:

(a) receiving a first row and column address as output by the device;

(b) asserting the first row and column address at the RAS and CAS inputs;

(c) receiving a second row and column address as output by the device;

(d) changing the column address being asserted at the CAS input to correspond to the second column address;

(e) checking the second row address against the first row address; and

,

(f) reasserting the second row and column address at the RAS and CAS inputs if the second row address is not the same as the first row address.

5. The method of operating a DRAM memory subsystem of claim 4 including the step of:

aborting an access to the DRAM prior to reasserting the second row and column address at the RAS and CAS inputs if the second row address is not the same as the first row address.

6. The method of operating a DRAM memory subsystem of claim 4 wherein there are a plurality of the DRAMs each identifiable by a bank number and the device includes a bank address as part of each row and column address for data to be accessed and additionally comprising the steps of:

(a) storing the presently being asserted row address for each blank in a memory table;

(b) changing the column address being asserted at the CAS input on the DRAM indicated by the bank address portion of a second address from the device to correspond to the second column address; and

,

(c) checking the second row address against the first row address as stored in the memory table for the bank indicated by the bank address portion of second address from the device.

7. The method of accessing a plurality of DRAMs in the static column mode by an instruction processor to provide minimum wait state accessing thereby comprising the steps of:

(a) having the instruction processor emit each instruction address as an address containing a bank number field, a row address field, and column address field;

(b) providing a table for storing a set of open pages being the current row address for each bank where a bank is associated with a respective one of the plurality of DRAMs;

(c) for each instruction address emitted from the instruction processor to effect a memory access in a static column mode, determining whether there is a match between the row address stored in the table and the row address emitted from the instruction processor employing the bank number as an index into the table of open pages;

(d) if the two addresses match, continuing the memory acess to an indicated bank in a continuing static column mode using the row and column addresses as presently asserted from the instruction address emitted from the instruction processor; and

,

(e) if the two addresses do not match, overwriting the old address for the indicated bank in the table with the new row address and continuing the memory acess by beginning a new static column mode access to the indicated bank by reasserting the row and column addresses from the instruction address emitted from the instruction processor.

8. The method of claim 7 and additionally comprising the step of:

aborting the access in progress if the two addresses do not match prior to beginning the new static column mode access to the indicated bank.

9. The method of claim 8 and additionally comprising the step of:

advising the instruction processor that the access in progress is being aborted and being begun again.

10. In a DRAM memory subsystem having a DRAM comprised of rows and columns and operable in a static column mode in response to address requests from a high performance memory accessing device outputting a series of row and column addresses for data to be accessed, the method of operation to provide minimum wait state accessing comprising the steps of:

(a) beginning each new access request from the device in a continuing static column mode access by only changing the column address;

(b) checking the row address being employed in the continuing static column mode access against the row address of the new access request;

(c) continuing with the current continuing static column mode access if the row addresses are the same; and

,

(d) terminating the current continuing static column mode access and beginning a new static column mode access with the row and column addresses of the new access request if the row addresses are not the same.

11. The improved method of operation of a DRAM memory subsystem of claim 10 wherein the row and column addresses of each access request are asserted at RAS and CAS inputs of a DRAM and the steps comprise:

(a) receiving a first row and column address as output by the device;

(b) asserting the first row and column address at the RAS and CAS inputs;

(c) receiving a second row and column address as output by the device;

(d) changing the column address being asserted at the CAS input to correspond to the second column address;

(e) checking the second row address against the first row address; and

,

(f) reasserting the second row and column address at the RAS and CAS inputs if the second row address is not the same as the first row address.

12. The improved method of operation of a DRAM memory subsystem of claim 11 including the additional step of:

advising the device of aborting and retrying an access to the DRAM if the second row address is not the same as the first row address.

13. The improved method of operation of a DRAM memory subsystem of claim 11 wherein there are a plurality of the DRAMs each identifiable by a bank number and the device includes a bank address as part of each row and column address for data to be accessed and additionally comprising the steps of:

(a) storing the presently being asserted row address for each bank in a memory table;

(b) changing the column address being asserted at the CAS input on the DRAM indicated by the bank address portion of second address from the device to correspond to the second column address; and

,

(c) checking the second row address against the first tow address as stored in the memory table for the bank indicated by the bank address portion of second address from the device.