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High performance dynamic ram interface

  • US 4,937,791 A
  • Filed: 06/02/1988
  • Issued: 06/26/1990
  • Est. Priority Date: 06/02/1988
  • Status: Expired due to Term
First Claim
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1. A DRAM memory subsystem capable of minimum wait state accessing by a high performance device accessing outputting a series of row and column addresses for data to be accessed comprising:

  • (a) a DRAM comprised of rows and columns and operable in a static column mode in response to address requests asserted at RAS and CAS inputs thereof; and

    ,(b) access optimization logic means operably connected for receiving a first row and column address as output by the device, for asserting said first row and column address at said RAS and CAS inputs, for receiving a second row and column address as output by the device, for changing the column address being asserted at said CAS input to correspond to said second column address, for checking said second row address against said first row address, and for reasserting said second row and column address at said RAS and CAS inputs if said second row address is not the same as said first row address.

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