Thin-film transistor array used for liquid-crystal display device

• US 4,938,565 A
• Filed: 08/19/1988
• Issued: 07/03/1990
• Est. Priority Date: 08/21/1987
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Ichikawa, Shouji
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): MAI, HUY KIM
• Application Number:
  US07/234,357
• Time in Patent Office: 683 Days
• Field of Search: 350/332, 350/333
• US Class Current: 349/54
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2330/08 Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A thin-film transistor array used for a liquid crystal display device uses a plurality of transistor structures as switches between a video signal line and a pixel electrode which is controlled with a control signal applied through a scanning line, each of transistor structures having a plurality of thin-film transistors connected in series and parallel and having gates commonly connected to the same scanning line. An example of each transistor structure has four thin-film transistors and has a parallel connection of two sets of series connections of two thin-film transistors or a series connection of two sets of parallel connections of two thin-film transistors.

Claims

1. A thin-film transistor array formed on an insulating board having a plurality of electrical signal applying first lines and a plurality of electrical signal applying second lines orthogonally crossing said first lines, the array comprising a plurality of transistor structures each formed in a region of said insulating board corresponding to each one crossing point of said first lines and said second lines;

and a plurality of electrical elements connected in the array so as to use an electrical signal applied from one of said first and second lines through one of said transistor structures, each of said transistor structures including a plurality of thin-film transistors each having source, drain and gate electrodes, said thin-film transistors in each one of said transistor structures being respectively connected so that at least one parallel connection and at least one series connection of electrical paths between the source and the drain electrodes of said transistors are formed.

2. A thin-film transistor array as claimed in claim 1, wherein each one of said transistor structures is formed of first, second, third and fourth thin-film transistors, and wherein an electrical path between the source and the drain electrodes of said first and third thin-film transistors is connected in series to form a first series connection and the electrical paths between the source and the drain electrodes of said second and fourth thin-film transistors are connected in series to form a second series connection, said first and second series connections being connected with each other in parallel.

3. A thin-film transistor array as claimed in claim 2, wherein a connecting point of said first and third thin-film transistors in said first series connection is connected to another connecting point of said second and fourth thin-film transistors in said second series connection.

4. A thin-film transistor array as claimed in claim 1, wherein each one of said transistor structures includes first, second, third and fourth thin-film transistors, and wherein the electrical paths between the source and the drain electrodes of said first and second thin-film transistors are connected in parallel to form a first parallel connection, and the electrical paths between the source and the drain electrodes of said third and fourth thin-film transistors are connected in parallel to form a second parallel connection, said first and second parallel connections being connected to each other in series.

5. A thin-film transistor array board comprising:

an insulating board;

a plurality of video signal lines formed on said insulating board in parallel with one another;

a plurality of control signal lines formed on said insulating board in parallel with one another and to orthogonally cross said video signal lines;

a plurality of transistor structures formed on said insulating board, one of said transistor structures being disposed at respective crossing points of said video signal lines with said control signal lines, each of said transistor structures including an input portion connected to one of said video signal lines, an output portion, a control signal receiving portion connected to one of said control signal lines, and a plurality of thin-film transistors each having source, drain and gate electrodes, all of said gate electrodes being commonly connected to said control signal receiving portion, said thin-film transistors in each one of said transistor structures being connected so that a series connection and a parallel connection of electrical paths between the source and drain electrodes of said thin-film transistors are formed; and

a plurality of pixel electrodes formed on said insulating board, each of said pixel electrodes being connected to said output portion of one of said transistor structures.

6. A thin-film transistor array board as claimed in claim 5, wherein at least one of said transistor structures includes first, second, third and fourth thin-film transistors, said first and third thin-film transistors being connected in series to form a first series connection, said second and third thin-film transistors being connected in series to form a second series connection, and said first and second series connections being connected in parallel between said input and output portions of said transistor structures.

7. A thin-film transistor array board as claimed in claim 5, wherein at least one of said transistor structures include first, second, third and fourth thin-film transistors, said first and second thin-film transistors being connected in parallel to form a first parallel connection, said third and fourth thin-film transistors being connected in parallel to form a second parallel connection, and said first and second parallel connections being connected in series between said input and output portions of said transistor structures.