Method for forming a buried lateral contact

• US 4,939,104 A
• Filed: 11/17/1987
• Issued: 07/03/1990
• Est. Priority Date: 10/31/1984
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bordelon, Donald M., Pollack, Gordon P., Richardson, William F., Malhi, Satwinder S.
• Primary Examiner(s): Chaudhuri, Olik
• Application Number:
  US07/122,604
• Time in Patent Office: 959 Days
• Field of Search: 437/160, 437/161, 437/162, 437/52, 437/31, 437/203, 437/233, 156/657
• US Class Current: 438/561
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

The present invention is described in conjunction with the fabrication of a dRAM cell which an important application of the present invention. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell transistor is formed on the sidewalls of a substrate trench containing the cell capacitor; the word and bit lines cross over this trench. This stacking of the transistor on top of the capacitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells.

One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is stored on the polysilicon capacitor plate by an electrical connection of the source region with the polysilicon capacitor plate, which is provided by the described embodiment of the invention.

Another embodiment of the present invention is an interconnection between a surface conductor and the surface of the substrate. This embodiment uses a conductive plug formed between the conductor and the substrate to form an interconnection using a minimum of surface area of the substrate.

Claims

1. A method for forming an interconnection in an integrated circuit comprising the steps of:

providing a semiconductive substrate of a first conductivity type;

forming a cavity in said substrate;

forming an insulating layer on the walls of said cavity;

forming a conductive layer on said insulating layer;

forming a crevice between said conductive layer and said substrate by removing a portion of said insulating layer between said substrate and said conductive layer; and

filling said crevice with a conductive contacting material.

2. The method of claim 1 further comprising forming a region of a second conductivity type in said substrate adjacent to said conductivde contacting material.

3. A method as in claim 1 wherein said removed portion of said insulating layer is removed by liquid chemical etching.

4. A method as in claim 1 wherein said conductive material is polycrystalline silicon deposited by conformal deposition.

5. A method as in claim 4 wherein said conformal deposition is chemical vapor deposition.

6. A method as in claim 2 wherein said region of a second conductivity is formed by diffusion of dopant atoms from said conductive layer through said conductive contacting material into said substrate.