Method and apparatus for the generation of voltage pulses

• US 4,939,443 A
• Filed: 01/10/1989
• Issued: 07/03/1990
• Est. Priority Date: 01/11/1988
• Status: Expired due to Fees

• Current Assignee: Siemens Nixdorf Informationssysteme AG (Siemens AG)
• Original Assignee: Nixdorf Computer AG (Siemens AG)
• Inventors: Gotz, Manfred, Pollmeier, Werner
• Primary Examiner(s): Wong, Peter S.
• Application Number:
  US07/295,633
• Time in Patent Office: 539 Days
• Field of Search: 323/242, 323/244, 323/274, 323/280, 323/284, 323/288, 323/326, 323/283
• US Class Current: 323/284
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H03K 4/06 having triangular shape

Abstract

The present invention relates to a method and apparatus for the generation of voltage pulses for controlling the switching operation in switching power supplies. A voltage increase of a pulse generator is respectively started when reaching a first, lower threshold (A). Resetting of the voltage increase is carried out in free-running mode, when the voltage increase reaches a second (D) or a third (C) threshold lying between the first (A) and the second (D) one. In sync mode, the pulse edges occurring in the synchronization signal (V_sync) effect resetting of the voltage increase. The advantages of the invention lie in the fact that the switching current, occurring at the change form free-running mode to sync mode due to the frequency difference, is minimized and that the generator operates reliably.

Claims

1. A method for generating voltage pulses used to control the operation of a switching power supply of the type responsive to synchronizing signals for synchronizing the voltage pulses with a synchronization reference, comprising the steps of:

(A) generating a voltage pulse having an amplitude which normally increases from a first voltage value to a third voltage value in the absence of one of said synchronization signals;

(B) resetting the amplitude of the voltage pulse generated in step (A) to said first voltage value if said synchronization signal occurs during the increase of amplitude of the voltage pulse generated in step (A) from said first voltage value to said third voltage value;

(C) then, generating a voltage pulse having an amplitude which normally increases from said first voltage value to a second voltage value higher than said third voltage value; and

(D) resetting the amplitude of the voltage pulse generated in step (C) to said first voltage value if said synchronizing signal occurs during the increase of the amplitude of the voltage pulse generated in step (C) from the fourth voltage value to said second voltage value, wherein said fourth voltage value lies between said first and third voltage values.

2. The method of claim 1, wherein steps (C) and (D) are successively repeated to maintain synchronization of the generated voltage pulses with said synchronization reference.

3. The method of claim 1, wherein step (B) is performed by resetting the amplitude of the voltage pulse generated in step (A) to said first voltage value only when said synchronization signal occurs during the increase of the amplitude of the voltage pulse generated in step (A) from said fourth voltage value to said third voltage value.

4. The method of claim 1, wherein the resetting of steps (B) and (C) includes generally linearly reducing the amplitude of said voltage pulse over a preselected time period to said first voltage value.

5. A method for generating voltage pulses for controlling the switching operation of a switching power supply, of the type which generates a voltage pulse which starts from a first voltage threshold and normally increases until a higher second voltage threshold is reached whereupon said voltage pulse is reset, and wherein the voltage pulse is synchronized with a synchronization signal, comprising the steps of:

(A) resetting said voltage pulse, in the absence of the occurrence of said synchronization signal, when said voltage pulse reaches a third voltage threshold, wherein said third voltage threshold lies between said first and second voltage thresholds;

(B) resetting the amplitude of said voltage pulse, in the absence of the occurrence of said synchronization signal, when said voltage pulse reaches said second voltage threshold; and

,

(C) resetting said voltage pulse in response to the edge of said synchronization signal.

6. The method of claim 5, further including:

(D) resetting said voltage pulse if a first synchronization pulse edge occurs when the amplitude of said voltage pulse is between said fourth and third voltage thresholds, wherein said fourth voltage threshold lies between said first and third voltage thresholds.

7. The method of claim 6, further including:

(E) after step (D), generating a voltage pulse having an amplitude which starts from a first voltage threshold and, in the absence of said synchronizing pulse edge, normally increases in amplitude to said second voltage threshold.

8. The method of claim 7, further including:

(F) after step (E), resetting said voltage pulse if a synchronization pulse edge occurs when the amplitude of said voltage pulse is between said fourth and second voltage thresholds.

9. The method of claim 8, wherein said resetting of the amplitude of said voltage pulses includes decreasing said amplitude in a generally linear manner over a predetermined time period.

10. The method of claim 5, further including:

(D) resetting said voltage pulse if a first synchronization pulse edge occurs when the amplitude of said voltage pulse is between said first voltage threshold and said third voltage threshold.

11. The method of claim 10, further including:

(E) after step (D), generating a voltage pulse having an amplitude which starts from a first voltage threshold and, in the absence of said synchronizing pulse edge, normally increases in amplitude to said second voltage threshold.

12. The method of claim 11, further including:

(F) after step (E), resetting said voltage pulse if a synchronization pulse edge occurs when the amplitude of said voltage pulse is between said fourth and second voltage thresholds.

13. The method of claim 12, wherein said resetting of the amplitude of said voltage pulses includes decreasing said amplitude in a generally linear manner over a predetermined time period.

14. A circuit for generating a series of voltage pulses used to control the operation of a switching power supply of the type responsive to synchronizing signals for synchronizing said voltage pulses with a synchronization reference, and of the type including a bistable circuit for triggering and resetting said voltage pulses, and of the type having a first and second threshold circuit coupled with said bistable circuit for commanding the triggering and resetting said voltage pulses, comprising:

a third threshold circuit for comparing the magnitude of each one of said voltage pulses with a third reference value, said third reference value being greater than a first reference value associated with said first threshold circuit, and being less than a second reference value associated with said second threshold circuit;

a third logic circuit having an output responsive to an edge of said synchronization signal;

a first logic circuit responsive to said second and third threshold circuits, and said third logic circuit; and

,

a second logic circuit responsive to an edge of an output signal from said third logic circuit output and operative to disable an output of said third threshold circuit when an edge of one of said synchronizing signals occurs and operative to enable the output of said third threshold circuit when the amplitude of one of said series of voltage pulses exceeds the second reference value.

15. The circuit of claim 14, further including:

a fourth threshold circuit for comparing the amplitude of one of said series of voltage pulses with a fourth reference value which lies between said first and third reference values, said fourth threshold circuit being operatively coupled to said third logic circuit for disabling said third logic circuit when the amplitude of one of said series of voltage pulses lies below said fourth reference value and enabling said third logic circuit when the amplitude of one of said series of voltage pulses lies above said fourth reference value, wherein enabling and disabling said third logic circuit respectively cause said third logic circuit to be respectively responsive to, or not responsive to the edge of one of said synchronization signals.

16. The circuit of claim 15, wherein said second logic circuit includes a first bistable circuit having a clock input responsive to said synchronization signals and having a reset input responsive to a output of said second threshold circuit.

17. The circuit of claim 14, wherein said second logic circuit includes a first bistable circuit having a clock input responsive to said synchronization signals and having a reset input responsive to a output of said second threshold circuit.

18. The circuit of claim 17, wherein said third logic circuit includes a second bistable circuit having a clock input responsive to said synchronizing signals and having a reset responsive to a output of said fourth threshold circuit.

19. The circuit of claim 18, wherein said clock input of said second logic circuit is responsive to the output of said third logic circuit.

20. The circuit of claim 19, wherein said second logic circuit includes an inclusive OR element for enabling and disabling the output of said third threshold circuit as a function of the state of said first bistable circuit.

21. The circuit of claim 20, wherein the first logic circuit includes an AND gate.

22. The circuit of claim 21, further including a fourth logic circuit responsive to said first threshold circuit, fourth threshold circuit, and an output of said first bistable circuit, said fourth logic circuit operative to disable the output of said fourth threshold circuit during at least a first one of a sequence of said synchronization signals.

23. The circuit of claim 22, further including an AND gate and an OR gate, said OR gate being responsive to the output of said fourth threshold circuit and the output of said first bistable circuit, said AND gate being responsive to the output of said or gate and the output of said first threshold circuit.

24. A circuit for generating a voltage pulses used to control the operation of a switching power supply of the type which is responsive to synchronizing signals used to synchronizing said voltage pulses to the synchronizing signals, comprising:

means for generating said voltage pulses;

means responsive to the amplitude of said voltage pulse for sensing when the amplitude of one of said voltage pulses has exceeded each of a plurality of preselected voltage levels;

means coupled with said sensing means for detecting the occurrence of an edge of one of said synchronizing signals; and

,

means associated with said sensing and detecting means for enabling said generating means to be controlled by said sensing and detecting means.

25. The apparatus of claim 24, wherein said generating means includes a first bistable circuit and a current source and a current sink, said first bistable circuit being coupled with said current source and current sink such that in one stable state of said first bistable circuit, said current source is operative to produce a constant current and said current sink is operative to create a high impedance current path, and in the other stable state thereof, said first bistable circuit causes said current source to produce a high impedance current path and said current sink is operative to produce a constant current load.

26. The apparatus of claim 25, wherein said sensing means includes a plurality of electrical comparators each having an output and each respective comparator operable for comparing the magnitude of one of said voltage pulses with one of said associated reference values.

27. The apparatus of claim 26, wherein said detecting means includes a second and third bistable circuit, said second bistable circuit being enabled to respond to an edge of one of said synchronizing signals only if the amplitude of one of said voltage pulses has exceeded the output of a preselected one of said electrical comparators, and said third bistable circuit having an output which is operative to disable the output of a preselected one of said electrical comparators if said second bistable circuit responds to said synchronizing signal.

28. The apparatus of claim 27, wherein said detecting means further includes logic means responsive to at least two outputs of said plurality of electrical comparators and the inverse of the output of said third bistable circuit, said logic means enabling said second bistable circuit to respond to said synchronizing signal when the amplitude of said voltage pulse lies between two of the preselected reference values.

29. The apparatus of claim 27, wherein said enabling means includes,

an OR gate having two inputs and one output, and

an AND gate having three inputs and one output,

said OR gate inputs being respectively associated with,

the output of one of said plurality of electrical comparators, and

the inverse of the output of said third bistable circuit,

said AND gate inputs being respectively associated with,

the output of one of said plurality of electrical comparators,

an output of said second bistable circuit, and

the output of said OR gate,

the output of said AND gate commanding one of the two stable states of said first bistable circuit.