Circuit for generating dual-tone multi-frequency signals and high/low-tone signals

• US 4,939,470 A
• Filed: 03/02/1989
• Issued: 07/03/1990
• Est. Priority Date: 05/27/1988
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Seo-Won
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US07/317,757
• Time in Patent Office: 488 Days
• Field of Search: 379/361, 328/14, 340/825.48, 377/56
• US Class Current: 327/107
• CPC Class Codes: H04M 1/505 signals generated in digital form

Abstract

A circuit for generating dual-tone multi-frequency (DTMF) signals and high/low-tone signals from digital data with designating frequencies of high-tone or high-frequency group and frequencies of low-tone or low-frequency group, and at least one digital control signal. The circuit includes a signal controlling logic circuit for decoding the digital data in response to the digital control signal, a circuit for generating a fixed clock pulse, a frequency dividing circuit of low-frequency group for generating first clock pulses, a frequency dividing circuit of high-frequency group for generating second clock pulses, first clock device for generating a plurality of pulses having a duty cycle of 50% by dividing the first clock pulses, second clock device for generating a plurality of pulses having a duty cycle of 50% by dividing the second clock pulses, and a signal synthesizing circuit for synthesizing the dual-tone multi-frequency signals or high/low-tone signals of analog sine-wave deprived of higher-harmonic wave component by inputting the clock pulses of the odd frequency.

Claims

1. A circuit for generating dual-tone multi-frequency and high/low-tone signals from digital data, comprising:

a signal controlling logic circuit for decoding the digital data, in response to a digital control signal, to generate a plurality of low-frequency selecting decoding signals for selecting the frequency of a low-frequency group, a plurlaity of high-frequency selecting decoding signals for selecting the frequency of a high-frequency group, a low-frequency group enabling signal and a high-frequency group enabling signal;

a circuit means for generating first clock pulses exhibiting a fixed frequency;

a low frequency dividing circuit for generating second clock pulses having a second frequency of a fixed multiple of a particular frequency selected from said low-frequency selecting decoding signals by counting and decoding said first clock pulses;

a high frequency dividing circuit for generating third clock pulses having a third frequency of a fixed multiple of a particular frequency selected from said high-frequency selecting decoding signals by counting and decoding said first clock pulses;

first clock means, enabled by said low-frequency group enabling signal, for generating a plurality of fourth pulses having a duty cycle of 50% through division of said second clock pulses, said fourth pulses having an odd frequency component of a higher-harmonic wave;

second clock means, enabled by said high-frequency group enabling signal, for generating a plurality of fifth pulses having a duty cycle of 50% through division of said third clock pulses, said fifth pulses having an odd frequency component of a higher-harmonic wave; and

a signal synthesizing circuit coupled to said first and second clock means, for synthesizing dual-tone multi-frequency signals to eliminate said odd frequency higher-harmonic wave components of said fourth and fifth pulses upon reception of said fourth and fifth clock pulses.

2. A circuit as claimed in claim 1, wherein said first clock pulse provided by said circuit for generating said first fixed clock pulse has a frequency nearly adjacent to a common multiple of the dual-tone multi-frequency signals frequency-divided by a master clock.

3. A circuit as claimed in claim 1, wherein said fourth and fifth clock pulses are higher-harmonic wave clock pulses of odd frequency comprising a clock pulse of a fundamental wave frequency, a clock pulse of a third-higher-harmonic of the fundamental wave frequency and a clock pulse of a fifth-higher-harmonic of the fundamental wave frequency, and said multiple being substantially an integer of thirty.

4. A circuit as claimed in claim 3, wherein the digital data includes information for generating said fifth-higher-harmonic wave, and means for controlling the generation of said fifth-higher-harmonic wave.

5. A circuit as claimed in claim 3, wherein said signal synthesizing circuit comprises a low-pass filter having a capacitor connected between an output node and a reference potential, and a plurality of resistors connected between said output node and each of the input terminals of said third and fourth clock pulses of said fundamental wave frequency, third higher-harmonic wave frequency, and fifth higher-harmonic wave frequency of said fourth and fifth pulses.

6. A circuit as claimed in claim 5, wherein said low-pass filter bypasses the frequency component of a seventh-higher-harmonic wave.

7. A circuit as claimed in claim 2, wherein said fourth and fifth pulses are higher-harmonic wave clock pulses of odd frequency comprising a clock pulse of a fundamental wave frequency, a clock pulse of a third-higher-harmonic of the fundamental wave frequency and a clock pulse of a fifth-higher-harmonic of the fundamental wave frequency, and multiple being substantially an integer of 30.

8. A circuit as claimed in claim 7, wherein the digital data includes information for generating said fifth-higher-harmonic wave, and means for controlling the generation of said fifth-higher-harmonic wave.

9. A circuit as claimed in claim 8, wherein said signal synthesizing circuit comprises a low-pass filter having a capacitor connected betweeen an output node and a reference potential, and a plurality of resistors connected between said output node and each of the input terminals of said third and fourth clock pulses of said fundamental wave frequency, third higher-harmonic wave frequency, and fifth higher-harmonic wave frequency of said fourth and fifth pulses.

10. A circuit as claimed in claim 9, wherein said low-pass filter bypasses the frequency component of a seventh-higher-harmonic wave.

11. A circuit for generating dual-tone multi-frequency and high/low-tone signals from digital data, comprising:

signal controlling logic means for decoding the digital data, in response to a digital control signal, to generate a plurality of signals;

means for generating a first fixed clock pulse;

low frequency dividing means for generating second clock pulses from first signals generated by said signal controlling logic circuit by counting and decoding said first clock pusles;

high frequency dividing means for generating third clock pulses from second signals generated by said signal controlling logic circuit by counting and decoding said first clock pulses;

first clock generating means, enabled by a third signal generating means by said signal controlling logic circuit, for generating a plurality of fourth pulses through division of said second clock pulses of said low frequency dividing circuit, and said fourth pulses having an odd frequency component of a higher-harmonic wave;

second clock generating means, enabled by a fourth signal generated by said signal controlling logic circuit, for generating a plurality of fifth pulses through division of said third clock pulses of said high frequency dividing circuit, and said fifth pulses having an odd frequency component of a higher-harmonic wave; and

signal synthesizing means couple to said first and second clock means, for synthesizing the dual-tone multi-frequency signals upon reception of said fourth and fifth clock pulses genrated by said first and second clock generators to eliminate said odd frequency higher harmonic wave components.

12. A circuit as claimed in claim 11, wherein said first signals, generated by said signal controlling logic circuit, are a plurality of low-frequency selecting decoding signals for selecting the frequency of a low-frequency group or low-tone.

13. A circuit as claimed in claim 12, wherein said second signals, generated by said signal controlling logic circuit, are a plurality of high-frequency selecting decoding signals for selecting the frequency of a high-frequency group or high-tone.

14. A circuit as claimed in claim 13, wherein said third signal, generated by said signal controlling logic circuit, is a low-frequency group enabling signal for enabling said first clock generator and said fourth signal, generated by said signal controlling logic circuit, is a high-frequency group enabling signal for enabling said second clock generator.

15. A circuit as claimed in claim 14, wherein said second pulses generated by said low-frequency dividing circuit have the frequency of a fixed multiple of a particular frequency selected from said low-frequency selecting decoding signals.

16. A circuit as claimed in claim 15, wherein said third pulses generated by said high-frequency dividing circuit have the frequency of a fixed multiple of a particular frequency selected from said high-frequency selecting decoding signals.

17. A circuit as claimed in claim 16, wherein said first clock pulse has a frequency close in value to a common multiple of the dual-tone multi-frequency and high/low-tone signals frequency-divided by a master clock.

18. A circuit as claimed in claim 17, wherein said fourth and fifth pulses are higher-harmonic wave clock pulses of odd frequency comprising a clock pulse of the fundamental wave frequency, a clock pulse of a third-higher-harmonic wave frequency and a clock pulse of a fifth-higher-harmonic wave frequency, and its multiple is substantially an integer of thirty.

19. A circuit as claimed in claim 18, wherein the digital data includes information for generating the fifth-higher-harmonic wave, and means for controlling the generation of said fifth-higher-harmonic wave.

20. A circuit as claimed in claim 19, wherein said signal synthesizing circuit comprises a low-pass filter having a capacitor connected between an output node and a reference node and a plurality of resistors connected between said output node and each input terminal of said fourth and fifth clock pulses of said fundamental wave frequency, third higher-harmonic wave frequency, and fifth higher-harmonic wave frequency of said fourth and fifth pulses.

21. A circuit as claimed in claim 20, wherein said low-pass filter bypasses frequency components of a seventh-higher-harmonic wave.

22. A method for generating dual-tone multi-frequency and high/low tone signals comprising the steps of:

receiving data control signals and digital data through an input bus from a central processing unit;

decoding the data signals to generate low-frequency selecting decoding signals, high-frequency selecting decoding signals, low-frequency group enabling signals and high-frequency group enabling signals;

generating first and second clock pulses from said low-frequency selecting decoding signals and said high-frequency selecting decoding signals, respectively;

dividing the frequency of said first pulse to generate third clock pulses upon enabling by said low-frequency group enabling signal and dividing the frequency of said second clock pulse in said second clock generator to generate fourth clock pulses upon enabling by said high-frequency group enabling signals; and

;

attenuating the harmonics of said third and fourth pulses to produce said dual-tone multi-frequency signal or said high/low-tone signal.

23. A method as claimed in claim 22, wherein counting and decoding of fifth fixed clock pulses to produce said first and second clock pulses having a frequency of a fixed multiple of a particular frequency of said respective selecting decoding signals.

24. A circuit for generating dual-tone multi-frequency and high/low-tone signals from digital data, comprising:

input means for conducting input data, representing low frequency signals, high frequency signals, low frequency enable signals, high frequency enable signals, and fifth harmonic wave control signals, and control signals;

signal controlling logic for decoding said input data, in response to said first control signals, to generate a plurality of low-frequency selecting decoding signals for selecting the frequency of a low-frequency group, a plurality fo high-frequency selecting decoding signals for selecting the frequency of a high-frequency group, a low-frequency group enabling signal and a high-frequency group enabling signal;

circuit means for generating first clock pulses exhibiting a fixed frequency;

low frequency dividing means for generating second clock pulses having a second frequency of a fixed multiple of a particular frequency selected from said low-frequency selecting decoding signals by counting and decoding said first clock pulses;

high frequency dividing means for generating third clock pulses having a third frequency of a fixed multiple of a particular frequency selected from said high-frequency selecting decoding signals by counting and decoding said first clock pulses;

first clock means, enabled by said low-frequency group enabling signal, for generating a plurality of fourth pulses through division of said second clock pulses, said fourth pulses having an odd frequency component of a higher-harmonic wave;

second clock means, enabled by said high-frequency group enabling signal, for generating a plurality of fifth pulses through division of said third clock pulses, said fifth pulses havin an odd frequency component of a higher-harmonic wave; and

a signal synthesizing circuit coupled to said first and second clock means, for synthesizing dual-tone multi-frequency signals to eliminate said odd frequency higher-harmonic wave components of said fourth and fifth pulses upon reception of said fourth and fifth clock pulses.

25. A circuit as claimed in claim 24, wherein said first clock pulse provided by said circuit for generating said first fixed clock pulse has a frequency nearly adjacent to a common multiple of the dual-tone multi-frequency signals frequency-divided by a master clock.

26. A circuit as claimed in claim 25, wherein said fourth and fifth clock pulses are higher-harmonic wave clock pulses of odd frequency comprising a clock pulse of a fundamental wave frequency, a clock pulse of a third-higher-harmonic of the fundamental wave frequency and a clock pulse of a fifth-higher-harmonic of the fundamental wave frequency, and said multiple being substantially an integer of thirty.

27. A circuit as claimed in claim 26, wherein the data includes information for generating said fifth-higher-harmonic wave, and means for controlling the generation of said fifth-higher-harmonic wave.

28. A circuit as claimed in claim 27, wherein said signal synthesizing circuit comprises a low-pass filter having a capacitor connected between an output node and a reference potential, and a plurality of resistors connected between said output node and each of the input terminals of said third and fourth clock pulses of said fundamental wave frequency, third highher-harmonic wave frequency, and fifth higher-harmonic wave frequency of said fourth and fifth pulses.

29. A circuit as claimed in claim 28, wherein said low-pass filter bypasses the frequency component of a seventh-higher-harmonic wave.

30. A circuit for generating dual-tone multi-frequency and high/low-tone signals from digital data, comprising:

input means for conducting input data and input control signals;

signal controlling logic means for decoding said input data, in response to said digital control signals, to generate a plurality of frequency selecting decoding signals;

circuit means for generating first clock pulses exhibiting a fixed frequency;

frequency dividing means for generating second clock pulses having a second frequency of a fixed multiple of a particular frequency selected from said frequency selecting decoding signals by counting and decoding said first clock pulses;

clock means for generating a plurality of third pulses through division of said second clock pulses, said third pulses having an odd frequency component of a higher-harmonic wave; and

signal synthesizing means coupled to said clock means, for synthesizing dual-tone multi-frequency signals to eliminate said odd frequency higher-harmonic wave components of said third pulses upon reception of said third clock pulses.