Three-dimensional integrated circuit and manufacturing method thereof

• US 4,939,568 A
• Filed: 03/17/1989
• Issued: 07/03/1990
• Est. Priority Date: 03/20/1986
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kato, Takashi, Taguchi, Masao
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US07/325,122
• Time in Patent Office: 473 Days
• Field of Search: 357/49, 357/71, 357/43, 357/41, 357/68, 357/75, 357/59, 357/54
• US Class Current: 257/686
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/19041 being a capacitor

Abstract

The present invention is directed to a three-dimensional stacked IC and a method for forming a three-dimensional stacked IC on a base plate. The three-dimensional stacked IC includes a unit semiconductor IC, which has constituent ICs formed on either one surface or on both surfaces of a substrate. In addition, the unit semiconductor ICs have a plurality of conducting posts buried in and penetrating through the substrate and insulated therefrom. The unit semiconductor ICs have interconnection terminals provided on both sides of the substrate for connecting other unit semiconductor ICs or a base plate. By stacking plural unit ICs on the base plate, a very large scale IC can be fabricated. Each constituent IC is formed on a bulk silicon substrate, therefore excellent quality can be obtained. This can be also applied to the fabrication of a ROM structure such as a PROM or MASK ROM, using single unit semiconductor ICs, wherein a wiring for the ROM can be formed on the second surface of the substrate.

Claims

1. A semiconductor integrated circuit comprising:

a plurality of unit semiconductor integrated circuits stacked together, each of said unit semiconductor integrated circuits comprising;

a substrate having first and second surfaces, said second surface having a smooth mirror finish;

an integrated circuit including at least one of an active and passive functional element, formed on at least said first surface of said substrate;

a conducting post having first and second end portions, said conducting post penetrating through said substrate to said first and second surfaces, and insulated therefrom; and

a wiring, formed on said first and second surfaces of said substrate including said conducting post and said integrated circuit, being selectively connected to said integrated circuit and to said first and second end portions of said conducting post;

an insulating layer, formed on the surface of said unit semiconductor integrated circuits, for connecting two adjacent ones of said plurality of unit semiconductor integrated circuits; and

an interconnection terminal, formed in said insulating layer and extending to said wiring, for connecting said two adjacent ones of said plurality of unit semiconductor integrated circuits.

2. A semiconductor integrated circuit according to claim 1, wherein said integrated circuit is formed on said first and second surfaces of said substrate.

3. A semiconductor integrated circuit according to claim 1, wherein an indentation is formed in said substrate, surrounding one of the first and second end portions of said conducting post, wherein said insulating layer is formed in said indentation, and wherein said wiring is formed on said buried insulating layer and said one of the first and second end portions of said conducting post.

4. A semiconductor integrated circuit according to claim 1, wherein said insulating layer is formed of thermosetting resin.

5. A semiconductor integrated circuit according to claim 4, wherein said thermosetting resin is silylated polymethylsilsesquioxane (PMSS).

6. A semiconductor integrated circuit comprising:

a substrate having first and second surfaces, said second surface having a smooth mirror finish;

a field effect transistor (FET) formed on said first surface of said substrate, said FET having a source region, a drain region and a gate region;

a conducting post, having first and second end portions penetrating through said substrate to said first and second surfaces and insulated therefrom, said first end portion being selectively connected to one of said drain region and source region of said FET; and

a wiring formed on said second surface of said substrate and said conducting post and selectively connected to said second end portion of said conducting post.

7. A semiconductor integrated circuit according to claim 6, wherein said semiconductor integrated circuit is a PROM structure including a bit line, wherein a region of said FET not connected to said conducting post forms a memory cell, and wherein said wiring forms a power source wiring.

8. A semiconductor integrated circuit according to claim 6, wherein said semiconductor integrated circuit is a MASK ROM structure, wherein a region of said FET not connected to said conducting post is connected to a power source, and wherein said wiring forms a bit line of said MASK ROM, whereby bit information is written in dependence upon whether said bit line is connected to said conducting post.

9. A semiconductor integrated circuit according to claim 6, wherein an indentation is formed in said substrate, surrounding said second end portion of said conducting post, wherein an insulating layer is formed in said indentation, and wherein said wiring is formed on said buried insulating layer and selectively connected to said second end portion of said conducting post.

10. A semiconductor integrated circuit comprising:

a substrate having first and second surfaces, said second surface having a smooth mirror finish;

a first integrated circuit formed on said first surface of said substrate, said first integrated circuit including at least one of an active and passive functional element;

a second integrated circuit formed on said second surface of said substrate, said second integrated circuit including at least one of an active and passive functional element;

conducting posts, having first and second end portions and placed in through holes extending from said first surface to said second surface of said substrate and insulated from said substrate;

an insulating film formed inside the through holes in said substrate;

first and second insulating layers formed on said first and second surface of said substrate, respectively, through holes formed in portions therein located over said conducting posts;

first and second wiring layers formed on said first and second insulating layers, respectively, and said conducting posts;

first and second cover insulating layers formed on said first and second wiring and insulating layers, respectively, through holes being formed in portions therein; and

interconnection terminals, selectively formed in the through holes of said first and second cover insulating layers, one end of said interconnection terminals being connected to said respective wiring layers.

11. A semiconductor device according to claim 10, wherein said first and second cover insulating layers include an inner insulating layer and an outer insulating layer formed on said inner insulating layer.

12. A semiconductor integrated circuit according to claim 11, wherein said first and second insulating layers are formed of thermosetting silicon resin.

13. A semiconductor integrated circuit, comprising:

a plurality of unit semiconductor integrated circuits stacked together, each of said unit semiconductor integrated circuits, comprising;

a substrate having a first and second surfaces, said second surface having a smooth mirror finish;

an integrated circuit including at least one of an active and passive functional element formed at least on said first surface of said substrate;

a conducting post having first and second end portions, said conducting post placed in a through hole extending from said first surface to said second surface of said substrate and insulated from said substrate; and

a wiring formed on said first and second surfaces of said substrate, said conducting post, and said integrated circuit, being selectively connected to said integrated circuit and to the first and second end portions of said conducting post;

an insulating layer, formed on said unit semiconductor integrated circuits, for connecting adjacent ones of said plurality of unit semiconductor integrated circuits; and

an interconnection terminal formed in said insulating layer and extending to and contacting said wiring formed on said first and second surfaces, for connecting said two adjacent ones of said plurality of unit semiconductor integrated circuits.

14. A semiconductor integrated circuit comprising:

a plurality of unit semiconductor integrated circuits stacked together, each of said unit semiconductor integrated circuits comprising;

a substrate having first and second surfaces, said second surfaces having a smooth mirror finish;

an integrated circuit including at least one of an active and passive functional element, formed on at least said first surface of said substrate;

a conducting post having first and second end portions, penetrating through said substrate, and insulated therefrom; and

a wiring, formed on said first and second surfaces of said substrate and said integrated circuit, being selectively connected to said integrated circuit and to said first and second end portions of said conducting post;

an insulating layer, including at least a thermosetting resin layer, formed on an outermost surface of said unit semiconductor integrated circuits and having a flat surface, for connecting adjacent ones of said plurality of unit semiconductor integrated circuits; and

an interconnection terminal, formed in said insulating layer and penetrating through said thermosetting layer and extending to said wiring, for connecting said two adjacent ones of said plurality of unit semiconductor integrated circuits.

15. A semiconductor integrated circuit according to claim 14, wherein said thermosetting resin is silylated polymethylsilsesquioxane (PMSS).