Network and intelligent cell for providing sensing bidirectional communications and control
First Claim
Patent Images
1. A cell for a network which network provides for the sensing of conditions, communicating messages on said conditions and controlling objects based on said messages said cells communicating via at least one medium in said network, comprising:
- a processor for preparing and interpreting said messages;
interface means for interfacing between said processor and said medium and for performing at least one of the functions of sensing one of said conditions or controlling one of said objects;
said processor encoding said messages into segments of 6 bit codes, each of said segments containing 3 binary ones and 3 binary zeroes and means for converting groups of 6 bit codes received over said medium into 4 bit nibbles, said messages beginning with a preamble which comprises a first one of said segments of 6 bit code followed by a second one of said segments of 6 bit code;
said interfacing means for providing bit synchronization from said first one of said segments and segment synchronization from said second one of said segments;
whereby a cell is realized.
0 Assignments
0 Petitions
Accused Products
Abstract
A cell for a network which provides for sensing of conditions, communicating messages and controlling objects through messages encoded into segments of six bit codes each containing 3 binary ones and 3 binary zeros. The messages begin with one predetermined code which provides bit synchronization followed by a second predetermined code which provides byte synchronization.
98 Citations
6 Claims
-
1. A cell for a network which network provides for the sensing of conditions, communicating messages on said conditions and controlling objects based on said messages said cells communicating via at least one medium in said network, comprising:
-
a processor for preparing and interpreting said messages; interface means for interfacing between said processor and said medium and for performing at least one of the functions of sensing one of said conditions or controlling one of said objects; said processor encoding said messages into segments of 6 bit codes, each of said segments containing 3 binary ones and 3 binary zeroes and means for converting groups of 6 bit codes received over said medium into 4 bit nibbles, said messages beginning with a preamble which comprises a first one of said segments of 6 bit code followed by a second one of said segments of 6 bit code; said interfacing means for providing bit synchronization from said first one of said segments and segment synchronization from said second one of said segments; whereby a cell is realized. - View Dependent Claims (2)
-
-
3. A cell for use in a network which provides for sensing, communicating and controlling, said cells communicating via at least one medium in said network, comprising:
-
a processor for preparing and interpreting packets; interface means for interfacing between said processor and said medium; said processor for encoding said packets into segments of 6 bit codes, each segment containing 3 binary ones and 3 binary zeroes and for decoding packets having said segments containing 3 binary ones and 3 binary zeroes; said interface means for utilizing a first one of said segments for bit synchronization and said second one of a segments for segment synchronization; whereby a cell is realized. - View Dependent Claims (4)
-
-
5. A cell for use in a network having a plurality of said cells which asynchronously communicate with one another in said network through the transmission and reception of packets, comprising:
-
processing means for preparing said packets, for encoding said packets into segments of 6 bit coded segments each segment having three binary ones and three binary zeroes, for including at the beginning of each of said packets a preamble comprising a first predetermined one of said segments containing 3 binary ones and 3 binary zeroes, and for including after said preamble a second predetermined one of said segments containing 3 binary ones and 3 binary zeroes, and circuit means, coupled to said processing means, for providing bit synchronization from said first predetermined segments containing 3 binary ones and 3 binary zeroes and segment synchronization from said second predetermined segments containing 3 binary one and 3 binary zeroes. - View Dependent Claims (6)
-
Specification