Input stage for flash A/D converter

• US 4,940,980 A
• Filed: 05/05/1989
• Issued: 07/10/1990
• Est. Priority Date: 05/05/1989
• Status: Expired due to Fees

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Tice, Thomas E.
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): Logan, Sharon D.
• Application Number:
  US07/348,050
• Time in Patent Office: 431 Days
• Field of Search: 341/159, 341/118, 341/155
• US Class Current: 341/159
• CPC Class Codes: H03M 1/0604 at one point, i.e. by adjusting a single reference value, e.g. bias or gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/36 simultaneously only, i.e. parallel type

Abstract

A flash converter in which an input circuit is provided for maintaining a substantially constant collector-base voltage on the input emitter-followers, so as to obviate the distortion caused by variation of the input capacitance with input voltage. The driving source directly drives the base of the emitter-followers and, through a level-shift circuit, also drives the collectors of the emitter-follower transistors.

Claims

1. In a flash analog-to-digital converter having an input node, or terminal, for receiving an analog input voltage and a plurality of emitter-follower transistors, each emitter-follower transistor having a base electrode connected to said input terminal and an emitter electrode connected to a comparator circuit, the improvement comprising:

each of said emitter-follower transistors having a collector electrode connected to a terminal for connection to a means for providing thereto a voltage offset by a constant amount from the analog input voltage.

2. A flash analog to-digital converter comprising:

a. a plurality of input stages connected in parallel to an input node for receiving an analog input voltage;

b. a like plurality of comparator stages, each input stage driving a corresponding one of the comparator stages;

c. each input stage comprising an emitter-follower transistor having a base electrode connected to the input node and an emitter electrode connected to drive the corresponding comparator stage;

d. offset means connected to the input node to supply a voltage offset from the analog input voltage by a constant value; and

e. said offset means being connected to drive in parallel the collector electrodes of said emitter-follower transistors.

3. The converter of claim 2, wherein the offset means comprises a level-shifting circuit having an input connected to the input node and an output connected to drive the input of a buffer amplifier, the buffer amplifier having an output driving in parallel the collectors of the emitter-follower transistors.

4. A flash analog-to-digital converter comprising:

a. a plurality of input stages connected in parallel to an input node for receiving an analog input voltage;

b. means for supplying the analog input voltage, including an analog signal source, a first buffer amplifier connected to receive the output of the analog signal source, and a first resistance connected between the output of the buffer amplifier and the input node;

c. a like plurality of comparator stages, each input stage driving a corresponding one of the comparator stages;

d. each input stage comprising an emitter-follower transistor having a base electrode connected to the input node and an emitter electrode connected to drive the corresponding comparator stage;

e. offset means connected to the analog source to supply a voltage offset from the output of the analog source by a constant value; and

f. said offset means being connected operatively to drive the collector electrodes of said emitter-follower transistors.

5. The converter of claim 4 further including a cascode transistor for each emitter-follower transistor, the emitter electrode of the cascode transistor being connected to the collector electrode of a respective one of the emitter-follower transistors, the collector electrode of the cascode transistor being connected to a supply voltage substantially greater than the voltage at the base of the cascode transistor, and the the offset means including a level shift circuit connected to receive the output of the analog source, a second buffer connected to receive the output of the level shift circuit, and a second resistor connected between the output of the second buffer and the base of the cascode transistor.