Semiconductor devices exhibiting minimum on-resistance

• US 4,941,026 A
• Filed: 08/26/1988
• Issued: 07/10/1990
• Est. Priority Date: 12/05/1986
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: General Electric Company
• Inventors: Temple, Victor A. K.
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US07/239,014
• Time in Patent Office: 683 Days
• Field of Search: 357/23.4, 357/23.8, 357/55, 357/56, 357/86, 357/58
• US Class Current: 257/333
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Abstract

An improved conductivity vertical channel semiconductor device includes an insulated gate electrode disposed adjacent a substantial portion of the voltage supporting region. In response to an appropriate bias, the control electrode couples to the electric field originating on charges within the voltage supporting region to reorient the electric field associated with those charges toward the gate electrode and transverse to the direction of current flow through the device. Improved control of the electric field within the voltage supporting region allows the doping concentration, and hence the conductivity of the channel, to be improved without a concomitant decrease in breakdown voltage. Accordingly, the channel width and cell repeat distance of the improved device can be reduced, allowing for an improved current density to be established throughout an overall device cell structure. The charge control region of the voltage supporting layer exhibits an aspect ratio of 0.5.

Claims

1. A semiconductor device comprising:

a body of semiconductor material having first and second opposed major surfaces and including;

a drift layer of semiconductor material exhibiting a concentration X of dopant impurities therein;

a second layer of semiconductor material between said drift layer and said first major surface;

a trench extending into said body from said first major surface through said second layer and extending a distance L_t into said drift layer to define a pedestal portion of said body having a width W and including portions of said drift and second layers, said drift layer portion of said pedestal having an aspect ratio L_t /W which is greater than or equal to 0.5, an area charge density of WX greater than or equal to ε

E_AV /2q, wherein ε

is the permittivity of the semiconductor material, E_AV is the electric field strength at avalanche breakdown and q is the electron charge;

means associated with said drift layer portion of said pedestal for diverting electric field lines originating with said dopant impurities of said drift layer portion of said pedestal to thereby increase the voltage supporting potential of said drift layer portion of said pedestal and said device; and

a first main electrode disposed on said first major surface in ohmic contact therewith; and

a second main electrode disposed on said second major surface in ohmic contact therewith;

the main ON-state current path through said device extending between said first and second main electrodes and, when said device is in said ON-state, said pedestal portion of said drift layer is free of inversion layers.

2. The semiconductor device of claim 1 wherein said second layer is doped with one type conductivity impurities and said drift layer is doped with opposite type conductivity impurities, whereby a first PN junction is formed between said drift and second layers and wherein said device further includes:

a further region of opposite type conductivity disposed in said second layer portion of said pedestal and in ohmic contact with said second main electrode; and

an insulated gate disposed in said trench proximate said second layer;

wherein;

said insulated gate, in response to an appropriate bias, induces a channel in said second layer for conductively coupling opposite type conductivity carriers through said second layer between said further region and said drift layer;

said first PN junction is a voltage blocking junction in the off-state of said device when the voltage applied across said first and second main electrodes is of one polarity.

3. The semiconductor device of claim 2 wherein said second layer is doped with one type conductivity impurities and said drive layer is doped with opposite type conductivity impurities, whereby a first PN junction is formed between said drift and second layer and wherein said device further includes:

a further region of opposite type conductivity disposed in said second layer portion of said pedestal and in ohmic contact with said second main electrode; and

an insulated gate disposed in said trench proximate said second layer;

said means associated with said drift layer portion of said pedestal comprises an insulated gate substantially coextensive with said trench;

said insulated gate, in response to an appropriate bias, inducing a channel in said second layer for conductively coupling opposite type conductivity carriers through said second layer between said further region and said drift layer.

4. The semiconductor device of claim 3 wherein when a bias potential is applied across said first and second main electrodes of a plurality to reverse bias said first PN junction, and said gate electrode is biased at substantially the same potential as said second main electrode.

an imaginary, equipotential, surface within said pedestal is situated in said drift layer where each point on said equipotential surface is substantially equidistant from said insulated gate and said first junction and at its deepest penetration into said pedestal extends to a depth L_V into said drift layer, L_V being measured from said first junction;

and

said trench and insulated gate extend to a depth measured from said first junction which is greater than L_V.

5. The semiconductor device of claim 3 wherein said extension of said insulated gate electrode comprises an insulation layer disposed in said trench adjacent said drift layer and a gate electrode disposed in said trench adjacent said insulation layer.

6. The semiconductor device of claim 5 wherein said gate comprises a conductor selected from the group consisting of metal silicates and refractory metals.

7. The semiconductor device of claim 5 wherein said gate electrode substantially fills said trench.

8. The semiconductor device of claim 5 wherein said trench comprises a bottom adjacent said drift layer and said insulation layer comprises N portions, an N^th portion of said insulation layer disposed proximate said bottom and exhibiting a thickness T_N and an N-1^th portion of said insulation layer being more proximate said first surface than said N^th portion is, said N-1^th portion exhibiting a thickness T_N-1, wherein T_N is greater than T_N-1.

9. The semiconductor device of claim 8 wherein said trench includes a bottom surface and wherein a bottom portion of said insulation layer overlies said bottom surface and said bottom portion exhibits a thickness T_B wherein T_B is greater than T_N.

10. The semiconductor device of claim 2 wherein said means associated with said drift layer of said pedestal comprises a second insulated gate extending in said trench over a substantial portion of said trench proximate said drift layer.

11. The semiconductor device of claim 10 wherein said second insulated gate is discrete from said first insulated gate.

12. The semiconductor device of claim 10 wherein said second insulated gate comprises a plurality of discrete insulated gate portions.

13. The semiconductor device of claim 10 wherein said second insulated gate comprises a second insulation layer disposed adjacent said drift layer and a second gate electrode disposed thereon.

14. The semiconductor device of claim 10 wherein said second gate comprises polysilicon.

15. The semiconductor device of claim 10 wherein said gate electrode comprises a conductor selector from the group consisting of metal silicides and refractory metals.

16. The semiconductor device of claim 10 wherein said means associated with said drift layer portion of said pedestal includes means for coupling said second insulated gate electrode to a source of bias potential.

17. The semiconductor device of claim 1 wherein said second layer is doped with one type conductivity impurities and said drift layer is doped with opposite type conductivity type impurities, said device further including an insulated gate disposed in said trench proximate said second layer, said insulated gate, in response to an appropriate applied bias, depleting carriers from said pedestal portion of said second layer to prevent current flow through said second layer.

18. The semiconductor device of claim 17 wherein said insulated gate is substantially coextensive with said trench.

19. The semiconductor device of claim 18 wherein said trench extends through greater than 50% of the depth of said drift layer.

20. The semiconductor device of claim 19 wherein said insulated gate electrode comprises an insulation layer disposed in said trench adjacent said drift layer and a gate electrode is disposed in said trench adjacent said insulation layer.

21. The semiconductor device of claim 20 wherein said gate electrode comprises polysilicon.

22. The semiconductor device of claim 20 wherein said gate electrode comprises a conductor selected from the group consisting of metal silicides and refractory metals.

23. The semiconductor device of claim 20 wherein said gate electrode substantially fills said trench.

24. The semiconductor device of claim 20 wherein said trench comprises a bottom adjacent said drift layer and said insulation layer comprises N portions, an N^th portion of said insulation layer being disposed proximate said bottom and exhibiting a thickness of T_N and an N-1^th portion of said insulation layer being more proximate said first surface than said N^th portion is, said N-1^th portion exhibiting a thickness T_N-1, wherein T_N is greater than T_N-1.

25. The semiconductor device of claim 20 wherein said trench includes a bottom surface and wherein a bottom portion of said insulation layer overlies said bottom portion of said insulation layer overlies said bottom surface and said bottom portion exhibits a thickness T_B wherein T_B is greater than T_N.

26. The semiconductor device of claim 2 wherein said means associated with said drift layer portion of said pedestal comprises a second insulated gate extending in said trench over a substantial portion of said trench proximate said drift layer.

27. The semiconductor device of claim 26 wherein said second insulated gate is discrete from said first insulated gate.

28. The semiconductor device of claim 26 wherein said second insulated gate comprises a plurality of discrete insulated gate portions.

29. The semiconductor device of claim 26 wherein said second insulated gate comprises a second insulation layer disposed adjacent said drift layer and a second gate electrode disposed thereon.

30. The semiconductor device of claim 26 wherein said second gate comprises polysilicon.

31. The semiconductor device of claim 26 wherein said second gate electrode comprises a conductor selected from the group consisting of metal silicides and refractory metals.

32. The semiconductor device of claim 26 wherein said means associated with said drift layer portion of said pedestal includes means for coupling said second insulated gate to a source of bias potential

33. The semiconductor device of claim 1 wherein said means associated with said drift layer portion of said pedestal is disposed within said trench.

34. The semiconductor device of claim 1 wherein said trench partially surrounds said pedestal.

35. The semiconductor device of claim 1 wherein said trench surrounds said pedestal.

36. The semiconductor device of claim 1 wherein W is greater than E_AV /2qV_B.

37. The semiconductor device of claim 1 wherein X is greater than ε

(E_AV)² /2qV_B.

38. The semiconductor device of claim 1 wherein X is approximately equal to ε

E_AV /W.

39. The semiconductor device of claim 1 wherein X is less than ε

E_AV /W.

40. The semiconductor device of claim 1 wherein said drift layer of said pedestal comprises a first zone disposed atop a second zone, said first zone exhibiting a doping concentration of X₁ and being disposed entirely within said pedestal and said second zone exhibiting a doping concentration of X₂, a portion of said second zone being disposed within said pedestal wherein X₁ is greater than X₂.

41. The semiconductor device of claim 40 wherein drift layer has a length L parallel to the height of said pedestal, said first zone has a length L₁, said second zone has a length L₂ and wherein L₁ +L₂ +L and the sum of X₁ L₁ and X₂ L₂ divided by is greater than ε

(E_AV)² /2qV_B.

42. The semiconductor device of claim 41 wherein another portion of said second zone extends beneath said trench.

43. The semiconductor device of claim 42 wherein said drift layer further comprises a third zone, said third zone being disposed atop said first zone.

44. The semiconductor device of claim 43 wherein said third zone exhibits a doping concentration of X₃ and wherein X₃ is less than X₁.

45. The semiconductor device of claim 44 wherein said drift layer has a length L parallel to the height of said pedestal, said first zone has a length L₁, said second zone portion exhibits a length L₂ and said third zone portion exhibits a length L₃, and wherein the sum of X₁ L₁, X₂ L₂ and X₃ L₃ divided by L is greater than ε

(E_AV)² /2qV_B.

46. The semiconductor device of claim 45 wherein L₁ is substantially greater than L₂.

47. The semiconductor device of claim 1 wherein said drift layer portion of said pedestal comprises a first zone and a second zone, said first zone being adjacent said second layer and exhibiting a doping concentration of X₁, and said second zone exhibiting a doping concentration of X₂ where X₁ is less than X₂.

48. The semiconductor device of claim 47 wherein said first zone exhibits a length L₁ parallel to the height of said pedestal, said second zone exhibits a length L₂, wherein L₁ substantially greater than L₂.

49. The semiconductor device of claim 48 (8) wherein said drift layer exhibits a length L equal to L₁ +L₂ and the sum of X₁ L₁ plus X₂ L₂ divided by L is greater than ε

(E_AV)² /2qV.

62. The semiconductor device of claim 1 wherein:

said drift and second layers are both doped to one conductivity type; and

said second layer is more heavily doped than said drift layer.

50. A semiconductor device comprising:

a body of semiconductor material including first, second and third zones having alternating conductivity types, said first and third zones being of one type conductivity, said second zone being of an opposite type conductivity and forming first and second PN junctions with said first and third zones, respectively;

said body of semiconductor material having first and second opposed major surfaces, said first major surface being comprised of a portion of said first zone and a portion of said second zone, said body having a substantially vertical trench extending into said body from said first major surface and through said first and second zones and into the third zone to define a pedestal portion of said body including portions of said first, second and third zones, said trench extending a length L_t into said third zone, said third zone portion of said pedestal having a width W and an aspect ratio of L_t /W which is greater than or equal to 0.5 throughout said pedestal;

an insulation layer disposed in said trench on said portions of said first, second and third zones exposed by said trench;

a gate electrode disposed in said trench adjacent said insulation layer and coextensive with said second zone and extending past said second junction and substantially covering said exposed portion of said third zone;

a first main electrode disposed on said first major surface in ohmic contact with said first zone; and

a second main electrode disposed on said second major surface in ohmic contact therewith;

the main ON-state current path through said device extending between said first and second main electrodes.

51. The semiconductor device of claim 50 further including means for coupling said gate electrode to an off-state bias potential for, in response to an off-state bias potential of appropriate polarity and magnitude, coupling the electric field associated with a substantial portion of said third zone portion of said pedestal to said gate electrode in a manner to increase the reverse breakdown voltage of said device.

52. The semiconductor device of claim 51 wherein said third zone is heavily doped.

53. The semiconductor device of claim 51 wherein said trench, insulation layer and gate electrode overlap at least 50% of said exposed portion of said third zone.

54. The semiconductor device of claim 51 wherein said gate electrode comprises first and second portions, said first portion being coextensive with at least said second zone and said second portion being coextensive with a substantial portion of said third zone.

55. The semiconductor device of claim 51 wherein said trench includes a bottom surface, and said insulation layer and said gate electrode overlie said bottom surface of said trench.

56. The gate semiconductor device of claim 51 wherein said trench includes a smoothly rounded corner.

57. The semiconductor device of claim 51 wherein said first main electrode is disposed in ohmic electrical contact with said second zone, said first main electrode thereby shorting said first PN junction at said first major surface.

58. The semiconductor device of claim 51 further including a fourth zone of opposite type conductivity adjacent said third zone and forming a third PN junction therewith.

59. The semiconductor device of claim 51 wherein said insulation layer comprises a first portion having a thickness T₂ proximate said second zone and a second portion having a thickness T₃ proximate said second junction and said third zone wherein T₃ is greater than T₂.

60. The semiconductor device of claim 51 wherein said insulation layer comprises N portions wherein the N^th portion is deep within the trench adjacent said third zone and an N-1^th portion is closer to the first major surface than said N^th portion is and exhibits a thickness T_N-1 and the N^th portion exhibits a thickness T_N, and wherein T_N is greater than T_N-1.

61. The semiconductor device of claim 51 wherein said insulation layer includes a transition region wherein the thickness of said insulation layer gradually increases from a thickness T₂ adjacent said second zone to a thickness T₃ adjacent said third zone.

63. The semiconductor device of claim 58 wherein said second main electrode is disposed in ohmic contact with said fourth zone.