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PLL circuit with band width varying in accordance with the frequency of an input signal

  • US 4,942,370 A
  • Filed: 04/04/1989
  • Issued: 07/17/1990
  • Est. Priority Date: 04/08/1988
  • Status: Expired due to Fees
First Claim
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1. A phase loop (PLL) circuit comprising:

  • phase comparing means for receiving an input signal and an output clock signal, detecting a difference in phase between these two signals, and outputting a first signal according to said phase difference;

    proportional means for converting said first signal to a first voltage having an amplitude proportional to said phase difference;

    integral means for converting said first signal to a second voltage having an amplitude proportional to an integral value of said phase difference; and

    voltage-controlled oscillating meands for receiving said first and second voltages and generating said output clock signal having a frequency controlled by said first and second voltages,a frequency F0 of said output clock signal being represented by the following formula, ##EQU8## where said first and second voltages are respectively designated by V1 and V2, and the values, a, b, and c are constants.

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