Single chip integrated circuit computer architecture
First Claim
Patent Images
1. A computer system comprising:
- a single chip stored program digital computer implemented on a single integrated circuit chip, said single chip stored program digital computer including(1) an integrated circuit read only memory storing computer instructions, wherein said integrated circuit read only memory is implemented on said single integrated circuit chip;
(2) an integrated circuit alterable memory storing computer operands, wherein said integrated circuit alterable memory is implemented on said single integrated circuit chip; and
(3) an integrated circuit processing circuit coupled to the integrated circuit alterable memory and processing the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory, wherein said integrated circuit processing circuit is implemented on said single integrated circuit chip.
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Abstract
Microcomputer architecture is provided that facilitates a fully integrated circuit computer on a single integrated circuit chip. The architecture includes use of an integrated circuit ROM for program storage, an integrated circuit RAM or scratch pad memory for alterable operand storage, and integrated circuit logic. Additional architectural features include serial data communication, pulse modulated communication, eight bit instruction bytes, sixteen bit operand words, and shared I/O channels.
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Citations
41 Claims
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1. A computer system comprising:
a single chip stored program digital computer implemented on a single integrated circuit chip, said single chip stored program digital computer including (1) an integrated circuit read only memory storing computer instructions, wherein said integrated circuit read only memory is implemented on said single integrated circuit chip; (2) an integrated circuit alterable memory storing computer operands, wherein said integrated circuit alterable memory is implemented on said single integrated circuit chip; and (3) an integrated circuit processing circuit coupled to the integrated circuit alterable memory and processing the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory, wherein said integrated circuit processing circuit is implemented on said single integrated circuit chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A stored program data processor comprising:
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a single integrated circuit chip to implement said stored program data processor; an integrated circuit read only memory storing processor instructions, wherein said integrated circuit read only memory is implemented on said single integrated circuit chip; an integrated circuit alterable memory storing processed information, wherein said integrated circuit alterable memory is implemented on said single integrated circuit chip; an integrated circuit processor coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the information stored by said integrated circuit alterable memory in response to the instructions stored by said integrated circuit read only memory, wherein said integrated circuit processor is implemented on said single integrated circuit chip; and an integrated circuit transfer circuit transferring instruction control in response to a triple byte transfer instruction stored by said integrated circuit read only memory, wherein said integrated circuit transfer circuit is implemented on said single integrated circuit chip, and wherein said integrated circuit transfer circuit includes (a) a first accessing circuit coupled to said integrated circuit read only memory and accessing a first byte of a triple byte transfer instruction, (b) a first transfer circuit coupled to said first accessing circuit and generating a transfer signal in response to the first byte of the triple byte transfer instruction, (c) a second accessing circuit coupled to said integrated circuit read only memory and to said first transfer circuit and accessing a second byte and a third byte of the triple byte transfer instruction in response to the transfer signal, (d) a combining circuit coupled to said second accessing circuit and generating a double byte transfer address by combining said second byte and said third byte accessed by said second accessing circuit, and (e) a transfer circuit coupled to said combining circuit and transferring instruction control in response to the double byte transfer address. - View Dependent Claims (20, 21, 22, 26)
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23. A stored program data processor comprising:
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a single integrated circuit chip to implement said stored program data processor; an integrated circuit read only memory storing processor instructions, wherein said integrated circuit read only memory is implemented on said single integrated circuit chip; an integrated circuit alterable memory storing processed information, wherein said integrated circuit alterable memory is implemented on said single integrated circuit chip; an integrated circuit processor coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the information stored by said integrated circuit alterable memory in response to the instructions stored by said integrated circuit read only memory, wherein said integrated circuit processor is implemented on said single integrated circuit chip, and wherein said integrated circuit processor includes (a) a first accessing circuit accessing a single byte instruction stored by said integrated circuit read only memory, (b) a first execution circuit executing the single byte instruction accessed by said first accessing circuit, (c) a second accessing circuit accessing a double byte instruction stored by said integrated circuit read only memory, (d) a second execution circuit executing the double byte instruction accessed by said second accessing circuit, (e) a third accessing circuit accessing a triple byte instruction stored by said integrated circuit read only memory, and (f) a third execution circuit executing the triple byte instruction accessed by said third accessing circuit. - View Dependent Claims (24)
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25. A stored program data processor system comprising:
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an input device generating input business information and a single chip integrated circuit data processor processing data in response to a stored program, said single chip integrated circuit data processor including (a) an integrated circuit read only main memory storing a program, wherein said integrated circuit read only main memory is included on said single chip; (b) an integrated circuit alterable memory storing operands, wherein said integrated circuit alterable memory is included on said single chip; (c) an integrated circuit input circuit generating a processor input signal in response to the input business information generated by said input device in response to the program stored in said integrated circuit read only main memory, wherein said integrated circuit input circuit is included on said single chip; (d) an integrated circuit storing circuit storing an operand into said integrated circuit alterable memory in response to the program stored by said integrated circuit read only main memory and in response to the processor input signal generated by said integrated circuit input circuit, wherein said integrated circuit storing circuit is included on said single chip; (e) an integrated circuit processing circuit processing operands stored by said integrated circuit alterable memory in response to the program stored by said integrated circuit read only main memory, wherein said integrated circuit processing circuit is included on said single chip; and (f) an integrated circuit output circuit outputting business information in response to the program stored by said integrated circuit read only main memory in response to the processing of operands by said integrated circuit processing circuit, wherein said integrated circuit output circuit is included on said single chip.
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27. A computer system comprising:
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an input device generating a digital input signal; a single chip integrated circuit digital computer coupled to said input device and generating a digital output signal in response to the digital input signal generated by said input device, said single chip integrated circuit digital computer including; (a) an integrated circuit read only main memory included on said single chip and storing a computer program, (b) an integrated circuit alterable memory included on said single chip and storing computer operands, (c) an integrated circuit processing circuit included on said single chip and coupled to said integrated circuit alterable memory, to said integrated circuit read only memory, and to said input device and processing a computer operand stored by said integrated circuit alterable memory on the same chip in response to the computer program stored by said integrated circuit read only main memory on said single chip in response to the digital input signal, and (d) an integrated circuit output circuit included on said single chip and coupled to said integrated circuit read only memory and to said integrated circuit processing circuit and generating the digital output signal in response to the computer program stored by said integrated circuit read only main memory on said single chip and in response to the digital input signal responsive processing of a computer operand by said processing circuit on said single chip; and a process controller coupled to said integrated circuit output circuit and controlling a process in response to the digital output signal. - View Dependent Claims (28)
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29. A computer on a chip comprising:
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an integrated circuit chip having a computer implemented thereon; an integrated circuit main memory storing computer instructions, wherein said integrated circuit main memory is included on said integrated circuit chip; an integrated circuit operand memory storing operands, wherein said integrated circuit operand memory is included on said integrated circuit chip; and an integrated circuit processing circuit processing the operands stored by said integrated circuit operand memory in response to the instructions stored by said integrated circuit main memory, wherein said processing circuit is included on said integrated circuit chip. - View Dependent Claims (30, 31, 32, 33, 34, 35)
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36. An integrated circuit stored program computer comprising:
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an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; an integrated circuit processing logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and generating the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory; an integrated circuit interrupt input logic circuit generating an interrupt input signal; an integrated circuit transfer logic circuit coupled to said integrated circuit read only memory and to said integrated circuit interrupt logic circuit and accessing an interrupt instruction stored by said integrated circuit read only memory in response to the interrupt input signal; and an integrated circuit interrupt return logic circuit coupled to said integrated circuit alterable memory and to said integrated circuit interrupt input logic circuit and storing a return address in said integrated circuit alterable memory in response to the interrupt input signal.
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37. An integrated circuit stored program computer comprising:
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an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; an integrated circuit processing logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and generating the computer operands stored by said integrated circuit alterable memory in response to the instructions stored by said integrated circuit read only memory; an integrated circuit transfer logic circuit coupled to said integrated circuit read only memory and transferring instruction control in response to a triple byte transfer instruction stored by said integrated circuit read only memory, said integrated circuit transfer logic circuit including (a) a first accessing circuit accessing a first byte of a triple byte transfer instruction stored by said integrated circuit read only memory, (b) a first transfer circuit coupled to said first accessing circuit and generating a transfer signal in response to said first byte of a triple byte transfer instruction, (c) a second accessing circuit coupled to said first transfer circuit and accessing a second byte and a third byte of a triple byte transfer instruction stored by said integrated circuit read only memory in response to the transfer signal, (d) a combining circuit coupled to said second accessing circuit and generating a double byte transfer address by combining said second byte and said third byte of a triple byte transfer instruction, and (f) a second transfer circuit coupled to said combining circuit and transferring instruction control in response to the double byte transfer address. - View Dependent Claims (38)
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39. An integrated circuit stored program computer comprising:
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an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; an integrated circuit processing logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory, wherein said integrated circuit processing logic circuit includes (a) a first accessing logic circuit accessing a single byte computer instruction stored by said integrated circuit read only memory, (b) a first instruction execution logic circuit coupled to said first accessing logic circuit and executing the single byte computer instruction accessed by said first accessing logic circuit, (c) a second accessing logic circuit accessing the double byte computer instruction stored by said integrated circuit read only memory, (d) a second instruction execution logic circuit coupled to said second accessing logic circuit and executing the double byte computer instruction accessed by said second accessing logic circuit, (e) a third accessing logic circuit accessing a triple byte computer instruction stored by said integrated circuit read only memory, and (f) a third instruction execution logic circuit coupled to said third accessing logic circuit and executing the triple byte computer instruction accessed by said third accessing logic circuit.
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40. An integrated circuit stored program computer comprising:
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an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; and an integrated circuit processing logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory, wherein said integrated circuit processing logic circuit includes an inline logic circuit executing an inline instruction, said inline logic circuit including; (1) a first accessing logic circuit accessing an inline computer instruction byte stored by said integrated circuit read only memory, (2) a first execution logic circuit coupled to said first accessing logic circuit and generating an inline signal in response to an inline computer instruction byte accessed by ,said first accessing logic circuit, (3) a second accessing logic circuit coupled to said first execution logic circuit and accessing at least one inline operand byte stored by said integrated circuit read only memory in response to the inline signal, and (4) a second execution logic circuit coupled to said second accessing logic circuit and processing the at least one inline operand byte accessed by said second accessing logic circuit.
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41. An integrated circuit stored program computer comprising:
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an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; an integrated circuit processor coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory; and an integrated circuit indirect transfer logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and providing indirect transfer of program control, said indirect transfer means including; (1) a first accessing logic circuit accessing an indirect transfer computer instruction stored by said integrated circuit read only memory, (2) an indirect transfer logic circuit coupled to said first accessing logic circuit and generating an indirect transfer signal in response to an indirect transfer computer instruction accessed by said first accessing logic circuit, (3) a second accessing logic circuit coupled to said indirect transfer logic circuit and accessing an indirect transfer address stored by said integrated circuit alterable memory in response to the indirect transfer signal, and (4) a third accessing logic circuit coupled to said second accessing logic circuit and accessing an instruction stored by said integrated circuit read only memory in response to the indirect transfer address accessed by said second accessing logic circuit.
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Specification