Microprocessor with a cache memory in which validity flags for first and second data areas are simultaneously readable

• US 4,942,521 A
• Filed: 11/13/1987
• Issued: 07/17/1990
• Est. Priority Date: 11/14/1986
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd., Hitachi Microcomputer Engineering Limited (Hitachi, Ltd.)
• Original Assignee: Hitachi, Ltd., Hitachi Microcomputer Engineering Limited (Hitachi, Ltd.)
• Inventors: Hasegawa, Atsushi, Hanawa, Makoto, Nishimukai, Tadahiko
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Ray, Gopal C.
• Application Number:
  US07/119,919
• Time in Patent Office: 977 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/128
• CPC Class Codes: G06F 12/0862 with prefetch

Abstract

When the access is effected sequentially such as the prefetching of an instruction or the restoration of a register in the stack region, the retrieval is effected simultaneously for the consecutive addresses and the result is stored. When the consecutive addresses are to be accessed, the hit is determined relying upon the result that is stored without effecting the cache memory reference. In the case of mishit, the external memory is readily accessed to shorten the overhead time required for the cache memory reference. Therefore, the access time can be shortened in average.

Claims

1. A microprocessor comprising:

(a) an instruction execution block for executing instructions using data stored in a cache memory or in an external memory;

(b) a cache memory coupled to said instruction execution block and including at least first and second data in areas which are commonly accessed by an upper bit signal of an instruction fetch address generated from said instruction execution block, the respective first and second data areas in said cache memory being selectively specified by a lower bit signal of said instruction fetch address, and wherein each area of said first and second data areas in said cache memory includes data and a flag associated with the data which indicates whether or not said data is valid;

(c) first means for reading out a flag in said second data area when a flag in a commonly accessed first data area is read out in response to said upper bit signal and a lower bit signal of an instruction fetch address which specifies said first data area;

(d) second means coupled to said first means for latching information related to a flag of said second data area when a flag of said second data area is read out by said first means; and

(e) third means for reading out said information from said second means in response to a lower bit signal of said instruction fetch address which specifies said second data area when said second data area is consecutively accessed after said first data area is accessed.

2. A microprocessor comprising:

(a) an instruction execution block for executing instructions using data stored in a cache memory or in an external memory;

(b) a cache memory coupled to said instruction execution block and including at least first and second data areas which are commonly accessed by an upper bit signal of an instruction fetch address generated from said instruction execution block, the respective first and second data areas in said cache memory being selectively specified by a lower bit signal of said instruction fetch address, and wherein each area of said first and second data areas in said cache memory includes data and a flag associated with the data which indicates whether or not said data is valid;

(c) first means for reading out a flag in said second data area when a flag in a commonly accessed first data area is read out in response to said upper bit signal and said lower bit signal of said instruction fetch address;

(d) second means coupled to said first means for holding information related to said flag of said second data area read out by said first means; and

(e) third means for reading out said information from said second means in response to said lower bit signal of said instruction fetch address when said second data area is consecutively accessed after said first data area is accessed, wherein said cache memory includes;

a first stack of a plurality of rows of storage areas arranged in a column direction, each row including a first data area and a second data area; and

a second stack of a plurality of rows of storage areas arranged in a column direction, each row of said second stack storing address information corresponding to data stored in said first and second data areas in a corresponding row of said first stack.

3. A microprocessor according to claim 2, wherein said cache memory further includes means for comparing said upper bit signal of said instruction fetch address with said address information stored in said plurality of rows of said second stack, and means for selecting one of said plurality of rows in said first stack in accordance with a detected coincidence between said upper bit signal with said address information by said comparing means to read out the data stored in said first and second data areas in said selected row.

4. A microprocessor comprising:

(a) an instruction execution block for executing instructions using data stored in a cache memory or in an external memory;

(b) a cache memory coupled to said instruction execution block and including at least first and second data areas which are commonly accessed by an upper bit signal of an instruction fetch address generated from said instruction execution block, the respective first and second data areas in said cache memory being selectively specified by a lower bit signal of said instruction fetch address, and wherein each area of said first and second data areas in said cache memory includes data and a flag associated with the data which indicates whether or not said data is valid;

(c) first means for reading out a flag in said second data area when a flag in a commonly accessed first data area is read out in response to said upper bit signal and said lower bit signal of said instruction fetch address;

(d) second means coupled to said first means for holding information related to said flag of said second data area read out by said first means; and

(e) third means for reading out said information from said second means in response to said lower bit signal of said instruction fetch address when said second data area is consecutively accessed after said first data area is accessed, wherein said third means includes means for producing signals related to a cache hit or a cache mis-hit on the basis of flags read out of said first and second data areas.

5. A microprocessor comprising:

(a) an instruction execution block for executing instructions using data stored in a cache memory or in an external memory, including means for generating a request signal for the accessing of data stored in consecutive storage locations of said cache memory or said external memory;

(b) a cache memory coupled to said instruction execution block and including at least first and second data areas which are commonly accessed by an upper bit signal of an instruction fetch address generated from said instruction execution block, the respective first and second data areas being selectively specified by respective first and second values of a lower bit signal of said instruction fetch address, and wherein each area of said first and second data areas includes data and a flag associated with the data which indicates whether or not said data is valid;

(c) first means responsive to said upper bit signal and said first value of said lower bit signal of said instruction fetch address for simultaneously reading out the flags in said first data area and said second data area of said cache memory;

(d) second means coupled to said first means and responsive to said request signal from said instruction execution block and said first value of said lower bit signal of said instruction fetch address for holding information related to said flag of said second data area read out by said first means;

(e) third means responsive to said flag of said first data area read out by said first means and said request signal from said instruction execution block for generating a cache hit or a cache mis-hit signal for said data in said first data area; and

(f) fourth means responsive to said information held in said second means, said request signal from said instruction execution block and said second value of said lower bit signal of said instruction fetch address for generating a cache hit or cache mis-hit signal for said data in said second data area.

6. A microprocessor according to claim 5, wherein said cache memory includes:

a first stack of a plurality of rows of storage areas arranged in a column direction, each row including a first data area and a second data area; and

a second stack of a plurality of rows of storage areas arranged in a column direction, each row of said second stack storing address information corresponding to data stored in said first and second data areas in a corresponding row of said first stack.

7. A microprocessor according to claim 6, wherein said cache memory further includes means for comparing said upper bit signal of said instruction fetch address with said address information stored in said plurality of rows of said second stack, and means for selecting one of said plurality of rows in said first stack in accordance with a detected coincidence between said upper bit signal with said address information by said comparing means to read out the data stored in said first and second data areas in said selected row.

8. A microprocessor according to claim 7, further including selector means, responsive to a cache hit signal from said third means and said first value of said lower bit signal, for applying data read out of a first data area to said instruction execution block, and responsive to a cache hit signal from said fourth means and said second value of said lower bit signal, for applying data read out of a second data area to said instruction execution block.

9. A microprocessor comprising:

(a) an instruction execution block for executing instructions using data stored in a cache memory or in an external memory, said cache memory being coupled to said instruction execution block and including at least first and second data areas, an upper bit signal of an instruction fetch address generated from said instruction execution block accessing commonly said first and second data areas, the respective first and second data areas in said cache memory being selectively specified by a lower bit signal of said instruction fetch address, and each area of said first and second data areas in said cache memory including data and a flag associated with said data indicates whether or not said data is valid;

(b) first means for reading out the flag in said second data area when the flag in said first data area is read out in response to said upper bit signal and said lower bit signal of said instruction fetch address;

(c) second means for holding information related to said flag of said second data read out by said first means; and

(d) third means for reading out said information from said second means in response to said lower bit signal of said instruction fetch address when said second data area is consecutively accessed after said first data area is accessed, said third means including means for inhibiting the reading out operation of said information from said second means in response to a branch request signal.

10. A microprocessor according to claim 9, wherein said cache memory includes:

a first stack of a plurality of rows of storage areas arranged in a column direction, each row including said first data area and said second data area; and

a second stack of a plurality of rows of storage areas arranged in a column direction, each row of said second stack storing address information corresponding to data stored in said first and second data areas in a corresponding row of said first stack.

11. A microprocessor according to claim 10, wherein said cache memory further includes means for comparing said upper bit signal of said instruction fetch address with said address information stored in said plurality of rows of said second stack, and means for selecting one of said plurality of rows in said first stack in accordance with a detected comparison of said upper bit signal with said address information by said comparing means to read out the data stored in said first and second data areas in said selected row.

12. A microprocessor according to claim 9, wherein said third means includes means for producing signals related to a cache hit or a cache mis-hit on the basis of flags read out of said first and second data areas.