Integrated, microminiature electric to fluidic valve and pressure/flow regulator

• US 4,943,032 A
• Filed: 09/19/1988
• Issued: 07/24/1990
• Est. Priority Date: 09/24/1986
• Status: Expired due to Term

• Current Assignee: Stanford University
• Original Assignee: Stanford University
• Inventors: Zdeblick, Mark
• Primary Examiner(s): FOX, JOHN C
• Application Number:
  US07/246,497
• Time in Patent Office: 673 Days
• Field of Search: 137/9, 137/10, 137/486, 137/861, 137/596, 137/116.3, 251/11, 73/204, 357/26, 357/28, 338/22, 338/22 SD, 338/23, 338/24
• US Class Current: 251/11
• CPC Class Codes: F15C 3/04 using diaphragms using loose plates or foils F15C3/005; connection of valves to inflatable elastic bodies B60C29/00
• CPC Class Codes: F15C 5/00 Manufacture of fluid circuit elements; Manufacture of assemblages of such elements integrated circuits
• CPC Class Codes: F16K 2099/0074 using photolithography, e.g. etching
• CPC Class Codes: F16K 2099/008 Multi-layer fabrications
• CPC Class Codes: F16K 2099/0084 Chemistry or biology, e.g. "lab-on-a-chip" technology
• CPC Class Codes: F16K 2099/009 Fluid power devices
• CPC Class Codes: F16K 99/0001 Microvalves microdevices B81B1/00; manufacture or treatment of devices or systems in or on a substrate B81C1/00; microfluidic structures B01L3/5027; micropumps F04B19/006
• CPC Class Codes: F16K 99/0015 Diaphragm or membrane valves
• CPC Class Codes: F16K 99/004 using radiation
• CPC Class Codes: F16K 99/0044 using thermo-electric means
• CPC Class Codes: F16K 99/0061 actuated by an expanding gas or liquid volume
• CPC Class Codes: G02B 3/0006 Arrays G02B3/02, G02B5/188 take precedence
• CPC Class Codes: G02B 3/0012 characterised by the manufacturing method
• CPC Class Codes: G02B 3/14 of variable focal length
• CPC Class Codes: G02B 6/32 having lens focusing means positioned between opposed fibre ends with lens being an integral part of the single fibre end G02B6/262
• CPC Class Codes: G02B 6/3692 with surface micromachining involving etching, e.g. wet or dry etching steps surface micromachining involving subtractive techniques B81C1/00055
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: Y10T 137/2607 With pressure reducing inlet valve

Abstract

A pressure regulator integrated in a sandwich of pyrex and silicon wafers. A first integrated valve comprising a silicon wafer in which there is etched a cavity so as to leave a flexible membrane of silicon is sandwiched between two other wafers which are usually pyrex. One of the pyrex wafers has a resistor pattern etched thereon in a location such that the resistor pattern is enclosed by the walls of the cavity when the pyrex wafer is bonded to the silicon wafer. The other pyrex wafer has a valve seat etched adjacent to the membrane in the silicon wafer. The cavity is filled with a fluid which, when heated, raises the vapor pressure in the cavity so as to cause the membrane to flex and change the spacing between the membrane and the valve seat thereby regulating flow. A second integrated valve has the same structure. One of these valves is coupled to a high pressure source and the other is coupled to a low pressure sink. Both valves are coupled to an output channel which has a capacitive pressure sensor integrated therein. Signals from this pressure sensor are used to control the energy applied to the resistors in the first and second valves to vary the area of the channels through the two valves coupling the output channel to the high pressure and low pressure sources.

Claims

1. An integrated pressure regulator comprising:

a first integrated valve comprising;

a first wafer;

a second wafer having a first surface and a second surface and having a trench etched into said first surface deep enough to leave a flexible diaphragm of the material of said second wafer defined by the bottom wall of said trench and said second surface, said silicon wafer being bonded to said first wafer such that said trench defines a sealed cavity;

a material trapped in said cavity which has a boiling point above the highest ambient temperature that might be experienced;

means for increasing the temperature of said trapped material to said boiling point so as to move said diaphragm;

and wherein said first wafer is pyrex and said second wafer if silicon and further comprising a second pyrex wafer having a first and second surface, said first surface having an input channel and an output channel etched therein, said input channel and said output channel separated by a valve seat in the form of a wall separating said input channel from said output channel, said first surface being bonded to said second surface of said silicon wafer at substantially all points except a predetermined area surrounding where said diaphragm mates with said valve seat;

and wherein said input channel and said output channel each have a plurality of projecting fingers which are interdigitated and wherein said valve seat takes the form of a serpentine mesa which separates the fingers of the input channel from the output channel fingers;

and wherein said means for heating is a resistive material deposited on the surface of said first pyrex wafer which seals said trench to form said cavity so as to be included within the perimeter of said cavity such that current may be passed through said resistive material to heat the fluid in the cavity

wherein said first and second pyrex wafers are anodically bonded to said silicon wafer and wherein the surface of said valve seat which contacts said diaphragm is coated with a material which prevents anodic bonding between said diaphragm and said valve seat;

said first integrated valve having its input port for coupling to a high pressure source;

a second integrated valve comprising;

a first wafer;

a second wafer having a first surface and a second surface and having a trench etched into said first surface deep enough to leave a flexible diaphragm of the material of said second wafer defined by the bottom wall of said trench and said second surface, said silicon wafer being bonded to said first wafer such that said trench defines a sealed cavity;

a material trapped in said cavity which has a boiling point above the highest ambient temperature that might be experienced;

means for increasing the temperature of said trapped material to said boiling point so as to move said diaphragm;

and wherein said first wafer is pyrex and said second wafer is silicon and further comprising a second pyrex wafer having a first and second surface, said first surface having an input channel and an output channel etched therein, said input channel and said output channel separated by a valve seat in the form of a wall separating said input channel from said output channel, said first surface being bonded to said second surface of said silicon wafer at substantially all points except a predetermined area surrounding where said diaphragm mates with said valve seat;

and wherein said input channel and said output channel each have a plurality of projecting fingers which are interdigitated and wherein said valve seat takes the form of a serpentine mesa which separates the fingers of the input channel from the output channel fingers;

and wherein said means for heating is a resistive material deposited on the surface of said first pyrex wafer which seals said trench to form said cavity so as to be included within the perimeter of said cavity such that current may be passed through said resistive material to heat the fluid in the cavity

wherein said first and second pyrex wafers are anodically bonded to said silicon wafer and wherein the surface of said valve seat which contacts said diaphragm is coated with a material which prevents anodic bonding between said diaphragm and said valve seat;

said second integrated valve sharing the same silicon wafer and the same pyrex wafers as said first integrated valve and having said input port of said second integrated valve for coupling to a low pressure effluent sink;

an output port for coupling to said output channels of both said first and said second integrated valves; and

a pressure sensor coupled to said output port.

2. An apparatus as defined in claim 1 wherein said pressure sensor comprises a diaphragm formed in the silicon wafer shared by said first and second integrated valves, said diaphragm in fluid communication with said output port and forming an evacuated chamber between said diaphragm and said first pyrex wafer shared by said first and second integrated valves, said evacuated chamber having a first capacitor plate formed by a conductive coating on at least a portion of the surface of said first pyrex wafer within said cavity and having a second capacitor plate formed by a conductive coating on at least a portion of the surface of said diaphragm.

3. An integrated pressure regulator comprising:

a first wafer having first and second surfaces, said second surface having first and second resistor patterns formed thereon and having a first conductive film formed thereon;

a second wafer bonded to said first wafer and having first and second surfaces, said first surface having first and second trenches formed therein, said trenches having a depth sufficient to form first and second flexible diaphragms between the bottoms of said trenches and said second surface, and having a third trench formed in said first surface, the bottom of said third trench being covered with a second conductive film, and having a fourth trench formed in the second surface opposite said fist surface, said fourth trench formed deep enough that a flexible diaphragm is formed between the bottoms of said third and fourth trenches, said first and second trenches being formed at locations aligned with the locations of said first and second resistor patterns such that said patterns are within the cavities formed between said first and second wafers at the locations of said first and second trenches, said third trench being located such that when the first and second wafers are bonded together in a vacuum, an evacuated cavity with said first and second conductive films forming a capacitor with a vacuum dielectric is formed; and

a third wafer having first and second surfaces, said first surface being bonded to said second surface of said second wafer at predetermined locations and having a first pair of input and output channels formed in said first surface and separated by a first valve seat in the form of a wall between said input and output channels which said first diaphragm contacts but which is not bonded to said first diaphragm, said first surface also having a second pair of input and output channels separated by a second valve seat in the form of a wall between said input and output channels which said second diaphragm contacts but which is not bonded to said second diaphragm, said second surface having a hole formed therein passing through said third wafer to emerge from said first surface at a location which is fluid communication with said fourth trench.

4. An integrated pressure regulator comprising:

first and second integrated valves comprising;

a first semiconductor wafer having first and second parallel and opposite surfaces and having a first trench formed in said first surface so as to leave a first flexible diaphragm between the bottom of said trench and said second surface of said wafer and having a second trench formed in said first surface so as to leave a second flexible diaphragm between the bottom of said second trench and said second surface of said wafer, and having third and fourth trenches formed in said first and second surfaces, respectively, so as to form a diaphragm, the bottom of said third trench being coated with a conductive film;

a second wafer bonded so as to seal said first and second trenches to form said first and second cavities;

first and second resistor patterns formed on said second wafer so as to be within said first and second cavities, respectively;

a conductive film formed on said second wafer aligned with said third trench so as to form a capacitor with the conductive film on the bottom of said third trench;

fluid sealed in said first and second cavities that, when heated by current flowing through said first and second resistor patterns, raises the vapor pressure in said first and second cavities so as to flex said first and second diaphragms;

a third wafer bonded to said semiconductor wafer and having first and second valve seats formed thereon adjacent to said first and second diaphragms, and having first and second input channels formed thereon and coupled, respectively, to said first and second valve seats thereby forming first and second fluid passageways from first and second input ports, and having an output channel formed thereon so as to be coupled to both said first and second valve seats so as to form a fluid output passage for each of said first and second integrated valves.