Full-duplex modem using a single processor

• US 4,943,942 A
• Filed: 09/19/1986
• Issued: 07/24/1990
• Est. Priority Date: 09/19/1986
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Inventors: Dunnion, Dermot
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Kulik, Paul V.
• Application Number:
  US06/910,111
• Time in Patent Office: 1,404 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/200, 364/900, 375/8, 375/7, 375/9, 370/29, 370/32
• US Class Current: 375/222
• CPC Class Codes: H04L 5/143 for modulated signals H04L5/1469 takes precedence

Abstract

Method of scheduling execution of transmit-side and receive-side procedures by a single processor in a full-duplex modem. Buffers of minimal size are employed in conjunction with the processor to guarantee no errors in the signal processing procedures. In one embodiment, transmit-side procedures are given priority so that if a transmit-enable signal is received, a receive-side procedure being executed by the processor is interrupted to allow execution of the transmit-side procedure. This priority is most useful because transmit-side procedures execute more rapidly than do receive-side procedures.

Claims

1. A full-duplex modem receiving digital data (TD) signals to be transmitted as analog data signals (TC) and receiving analog data signals (RC) to be converted to received digital data signals (RD), said modem receiving a transmit-enable signal and a receive-enable signal, said modem comprising:

means for generating a plurality of transmitter clock signals;

means for generating a plurality of receiver clock signals;

means responsive to one of said transmitter clock signals, for receiving said TD signals and synchronously generating therefrom signals at a predetermined rate Tx1;

first means for temporarily storing a predetermined number (N_T) of said synchronous signals generated from said TD signals;

means responsive to one of said receiver clock signals, for receiving said RC signals and synchronously generating therefrom digital signals at a predetermined multiple (N_R) of a predetermined rate Rx1;

second means for temporarily storing said predetermined multiple N_R of said synchronous signals generated from said RC signals;

memory means for storing programs and data;

programmable digital processor means, operably connected to said memory means, responsive to said transmit- and receive-enable signals and responsive to at least one of said transmitter clock signals, and to at least one of said receiver clock signals, for sampling said temporarily-stored signals generated from said TD signals, for executing a transmit-side signal processing procedure thereon and for generating therefrom digitized transmit signals, for sampling said temporarily-stored signals generated from said RC signals, for executing a receive-side signal processing procedure thereon and for generating therefrom digitized receive signals;

third means reponsive to one of said transmitter clock signals for temporarily storing said digitized transmit signals;

means responsive to one of said transmitter clock signals for converting said temporarily-stored digitized transmit signals to said analog data signals (TC);

fourth means responsive to one of said receiver clock signals for temporarily storing said digitized receive signals; and

means responsive to one of said receiver clock signals for receiving said temporarily-stored digitized receive signals and synchronously generating therefrom said received digital data signals (RD) at said predetermined rate Rx1;

wherein said processor means have a maximum, minimum, respectively, delay between reception of said transmit-enable signal and beginning execution of said transmit-side processing procedures of Δ

_T, Δ

_T, respectively, and has a maximum, minimum, respectively, delay between reception of said receive-enable signal and beginning execution of said receive-side processing procedures of Δ

_R, Δ

_R, respectively, wherein said third means temporarily stores N_T +N_T ·

(Tx1)·

(Δ

_T -Δ

_T) digitized transmit signals and wherein said second means temporarily stores N_R +N_R ·

(Rx1)·

(Δ

_R -Δ

_R) of said RC signals whereby said programmable digital processor means executes said transmit-side and said receive-side signal-processing procedures in time according to a predetermined schedule.