Method and apparatus for translating rectilinear information into scan line information for display by a computer system

• US 4,945,497 A
• Filed: 12/20/1988
• Issued: 07/31/1990
• Est. Priority Date: 12/20/1988
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Priem, Curtis, Malachowsky, Chris
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Jaffe, Michael A.
• Application Number:
  US07/287,493
• Time in Patent Office: 588 Days
• Field of Search: 364/518, 364/521, 364/522, 340/727, 340/724, 340/747, 340/723
• US Class Current: 345/428
• CPC Class Codes: G09G 5/391 Resolution modifying circuits, e.g. variable screen formats
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A circuit which computes the scan position of any pixel on the display as the sum of the number of scan lines multiplied by the number of pixels per scan line plus the number of pixels on the scan line to the particular position using an adder for a changing portion of the computation and an incrementer for a constant portion of the computation and combining the two of these to produce a result which accomplishes in a relatively economic fashion what would normally require an inordinate number of gates to obtain a variety of screen resolutions which are not simply powers of two multiples of one another.

Claims

1. An apparatus for translating addresses corresponding to rectilinear coordinates of a plurality of scan line masks generated by a mask generator into addresses for a linear memory interface for the rapid display of an image on an output display, comprising:

an adder coupled to said linear memory interface for providing a plurality of resolutions upon which said scan line masks may be displayed on said output display;

first circuit means connected to said adder for providing a first input thereto, said first circuit means being coupled to said mask generator for receiving a Y rectilinear value therefrom, said first circuit means being further provided with an input indicative of a desired resolution for said output display;

second circuit means coupled to said adder for providing a second input thereto, said second circuit means being coupled to said mask generator for receiving a Y rectilinear value therefrom, said second circuit being further provided with an input indicative of a desired resolution for said output display; and

third circuit means coupled to said mask generator for providing a third input to said adder, said third circuit means being coupled to said mask generator for receiving a Y rectilinear value and the highest bit value of a X rectilinear value therefrom, said third input being provided with the value of the first ten bits of a X rectilinear coordinate.

2. An apparatus as defined in claim 1, wherein said resolutions are other than a power of two multiple of said resolution.

3. An apparatus as defined in claim 1, wherein said first circuit means is a multiplexer, said multiplexer providing a multiple of said Y rectilinear value as said first input to said adder.

4. An apparatus as defined in claim 1, wherein said second circuit means is a multiplexer, said multiplexer providing a multiple of said Y rectilinear value as said second input to said adder.

5. An apparatus as defined in claim 1, wherein said third circuit means is an incrementer, said incrementer providing a multiple of said Y rectilinear value as part of said third input to said adder.

6. An apparatus as defined in claim 1, wherein said Y rectilinear value comprises the Y rectilinear coordinate of said scan line describing said image.

7. An apparatus as defined in claim 1, wherein said X rectilinear value comprises the left most x-coordinate of said scan line describing said image.

8. The third input as defined in claim 1 further comprises a sum of said X rectilinear value and a multiple of said Y rectilinear value.