Communication protocol for a three nodes system having dedicated connections and bit indicating function of exchanged message

• US 4,947,317 A
• Filed: 10/12/1988
• Issued: 08/07/1990
• Est. Priority Date: 10/12/1988
• Status: Expired due to Term

• Current Assignee: Pitney Bowes Incorporated World Headquarters Stamford CT
• Original Assignee: Pitney Bowes Incorporated (Böwe Systec AG)
• Inventors: Lee, David K., DiGiulio, Peter C.
• Primary Examiner(s): Lee, Thomas C.
• Application Number:
  US07/256,811
• Time in Patent Office: 664 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 371/32, 375/117, 370/48, 370/49
• US Class Current: 710/105
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A communication network comprised of a first, second and third controller node. Each of the controller nodes includes a microprocessor for generating and receiving data messages. The first nodes has a transmit pin in line communication with the receive pin of the second nodes and has a receive pin in line communication with the transmit pin of the second node. The third controller receive pin is in line communication with the transmit pin of the first node and its transmit pin is in line communication with the receive pin of the first node. The microprocessors are programmed to respond to and generate suitable formatted data message bytes. The microprocessors are further programmable to respond only to a unique address-command data message byte from the message source node. The microprocessor will then issue a reply message byte to the destination node. The transmitting node will then send a data message. Where the receiving node is the third node, a data message from the third node must then follow. The protocol is software implemented and includes means of detecting a message error and resolving transmission line content.

Claims

1. A communication network, comprising:

a first, second and third controller node;

each of said controller nodes having a transmit pin, a receive pin and processor means for generating data messages and causing said data messages to be delivered to said transmit pin and receiving data messages delivered to said receive pin, said transmit pin of said first controller node in line communication with said receive pin of said second controller node and said receive pin of said first controller node in line communication with said transmit pin of said second controller node, said receive pin of said third controller node in line communication with said transmit pin of said first controller node and said transmit pin of said third controller node in line communication with the receive pin of said first controller node;

each said processor means being programmed to respond to and generate a plurality of data message bytes, each data message byte having one start bit, eight data bits, one programmably settable bit and one stop bit;

each said processor means further programmed to respond only to a unique address-command data message byte, said address-command byte having said settable bit set, each said processor means to then generate in response thereto a reply message byte with the ninth bit not set, each said means processor to then receive a message count byte followed uninterrupted by a plurality of data message bytes, said message count byte and said data message bytes having the ninth bit not set, each said processing means upon receiving a complete data message conforming to the received count of said count byte to generate an acknowledgement byte;

said processor means of said first and second controller nodes being further programmed to generate a unique address-command data message byte, said address-command byte having said settable bit set, said processor means of said first and second controller nodes to then receive a reply message byte, said reply message byte to have the ninth bit not set, said processor means of said first and second controller nodes to then transmit a message count byte followed uninterrupted by a plurality of data message bytes, said count byte and said data message bytes having the ninth bit not set, said processor means of said first and second controller nodes to then receive an acknowledgement byte indicating whether the received message was error free;

said processor means of said third controller node being further programmed after generating such acknowledgement byte to generate a message count byte followed uninterrupted by a plurality of data message bytes, said message count byte and said data message bytes having the ninth bit not set, said processor means of said third controller node to then receive an acknowledgement byte indicating whether the received message was error free.

2. A communication network as claimed in claim 1, further comprising:

said processor means of said second controller node further programmable should said second controller node initiate a transmission to said first controller node receive a reply byte message with the ninth bit set said second controller node processor means will abort said transmission and wait for a predetermined amount of time and subsequent thereto attempt said transmission.

3. A communication network as claimed in claim 2, wherein each said processor means further comprises:

error message detection means for detecting whether said data bytes received are error free such that should said data bytes contain an error said processor means to generate a negative acknowledgement byte or should said data bytes contain no errors said processor means to generate a positive acknowledgement byte.

4. A communication network as claimed in claim 3, wherein said error message detection means comprises:

said message count byte containing a sequence number, said processor means being programmed to calculate a cyclic redundancy checksum as a function of the data bytes and compare said cyclic redundancy checksum with a checksum calculated as a function of said sequence number such that should said checksums match said data message is error free, should said checksums not match said data message contains a error.

5. A communication network, comprising:

a first, second and third controller node;

each of said controller nodes having a transmit pin, a receive pin and processor means for generating data messages and causing said data messages to be delivered to said transmit pin and receiving data messages delivered to said receive pin, said transmit pin of said first controller node pin in line communication with said receive pin of said second controller node and said receive pin of said first controller node in line communication with said transmit pin of said second controller node, said receive pin of said third controller node in line communication with said transmit pin of said first controller node and said transmit pin of said third controller node in line communication with the receive pin of said first controller node;

each said processor means being programmed to respond to and generate a plurality of data message bytes, each data message byte having one start bit, eight data bits, one programmably settable bit and one stop bit;

each said processor means being further programmed to respond only to a unique address-command data message byte, said address-command byte having said settable bit set, each said processor means to then generate in response thereto a reply message byte with the ninth bit not set, each said processor to then receive a message count byte followed uninterrupted by a plurality of data message bytes, said message count byte and said data message bytes having the ninth bit not set, each said processor upon receiving a complete data message conforming to the received count of said count byte to generate an acknowledgement byte;

said processor means of said first and second controller nodes being further programmed to generate a unique address-command data message byte, said address-command byte having said settable bit set, said processor means of said first and second controller nodes to then receive a reply message byte, said reply message byte to have the ninth bit not set, said processor means of said first and second controller nodes to then transmit a message count byte followed uninterrupted by a plurality of data message bytes, said count byte and said data message bytes having the ninth bit not set, said processor means of said first and second controller nodes to then receive an acknowledgement byte indicating whether the received message was error free;

said processor means of said third controller node being further programmed after generating said acknowledgement byte to generate a message count byte followed uninterrupted by a plurality of data message bytes, said message count byte and said data message bytes having the ninth bit not set, said processor means of said third controller node to then generate an acknowledgement byte indicating whether the received message was error free;

said processor means of said second controller node further being programmed such that should said second controller node initiate a transmission to said first controller node receive a reply byte message with the ninth bit set said second controller node processor means will abort said transmission and wait for a predetermined amount of time and subsequent thereto attempt said transmission.

6. A communication network as claimed in claim 5, wherein said processor means further comprises:

error message detection means for detecting whether said received data bytes are error free such that should said data bytes contain an error said processor means to generate a negative acknowledgement byte or should said data byte contain no errors said processor means to generate a positive acknowledgement byte.