Input/output controller incorporating address mapped input/output windows and read ahead/write behind capabilities

• US 4,947,366 A
• Filed: 10/02/1987
• Issued: 08/07/1990
• Est. Priority Date: 10/02/1987
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Johnson, William M.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Nguyen, Viet Q.
• Application Number:
  US07/104,722
• Time in Patent Office: 1,040 Days
• Field of Search: 364/200, 364/900 MS File, 364/900
• US Class Current: 710/3
• CPC Class Codes: G06F 13/404 with address mapping

Abstract

Methods and apparatus are set forth for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. The aforesaid transfer is accomplished in a manner that facilitates communication between the first and second set of devices while insulating the performance of the first set of devices from the comparatively lower performance of the second set of devices. According to the preferred embodiment of the invention, an input/output controller i.e., ("IOC") is disclosed that includes a set of address mapped I/O ports. The I/O ports may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting IOC interface between the Local Bus and Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance. The IOC may be used as part of a data transfer controller ("DTC") having other components, such as direct memory access components, or may be used independently for transferring data between unmatched buses in, for example, RISC and non-RISC systems and data transmission systems generally.

Claims

1. An input/output controller for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of relative lower performance devices is attached, wherein the transferring of data to and from said first and second buses facilitates communication between said first and second set of devices while preventing the performance of said first set of devices from being effected by the relatively lower performance of said second set of devices comprising:

(a) control means, coupled to said first bus and to said second bus, including at least one address mapped input/output port means, for providing direct access to said second set of devices by said CPU;

(b) means for interconnecting said first bus to said control means; and

(c) means for interconnecting said second bus to said control means;

wherein said input/output port means comprises means for performing address translation between a first bus address supplied to the input/output port means and a second bus address to be output to said second bus from the input/output port means.

2. An input/output controller as set forth in claim 1 wherein said means for interconnecting said second bus to said control means further comprises packing and funneling means, coupled to said control means, for accommodating variable width data transfers between said first bus and said second bus.

3. An input/output controller as set forth in claim 2 wherein said input/output controller includes a plurality of said input/output port means and further comprises means for prioritizing accesses to said plurality of input/output port means.

4. An input/output controller as set forth in claim 3 further comprising means for checking parity for both data and address transfers.

5. An input/output controller as set forth in claim 1 including a set of internal registers for controlling and maintaining the status of said input/output port means.

6. An input/output controller as set forth in claim 5 wherein said means for interconnecting said first bus to said control means further comprises means for initializing said set of registers.

7. An input/output controller as set forth in claim 1 further comprising means for performing overlapped I/O via said input/output port means.

8. An input/output controller as set forth in claim 1 further comprising means for performing data packing and unpacking.

9. An input/output controller as set forth in claim 1 further comprising means for swapping data packet location in words being transferred via the controller.

10. An input/output controller as set forth in claim 6 further comprising a plurality of signal paths used for carrying CPU and device generated signals to and from said set of internal registers, which serve to initialize and control data transfer operations.

11. An input/output controller as set forth in claim 10 wherein said plurality of signal paths comprise the pins of an integrated circuit package.

12. An input/output controller as set forth in claim 1 further comprising means for decoupling access to said second set of devices via said input/output port means by said CPU.

13. An input/output controller as set forth in claim 12 wherein said decoupling is accomplished via means for performing overlapped input/output.

14. An input/output controller as set forth in claim 2 further comprising means for determining if a first bus address supplied to said input/output port means by said first bus is within a preselected port means address space.

15. An input/output controller as set forth in claim 1 wherein said address translation is performed over a power of two range of addresses from a specified address of said first bus to an unrestricted range of addresses of said second bus.

16. An input/output controller as set forth in claim 15 wherein said means for performing said address translation further comprises means for masking out a preselected number of high order bits from the first bus address and replacing said bits with the same number of high order bits of the second bus address.

17. An input/output controller as set forth in claim 3 wherein said input/output port means further comprises means for multiplexing data to and from said packing and funneling means.

18. An input/output controller as set forth in claim 17 wherein each of said input/output port means further comprises a pack/funnel register for buffering data being transferred to and from said packing and funneling means by said input/output port means.

19. An input/output controller as set forth in claim 18 further including means for performing overlapped input/output, wherein said means for performing overlapped input/output further comprises:

(a) means for determining if a given input/output port means is enabled to perform a read ahead/write behind operation instead of direct read/write operation; and

(b) means for immediately responding to an access request on said first bus to a given input/output port means which is enabled to perform a read ahead/write behind operation even though an access by said second bus to said input/output port means may be in progress.

20. An input/output controller as set forth in claim 19 wherein said means for responding further comprises:

(a) means for latching an address of said first bus access;

(b) means for determining if said first bus access is a read; and

(c) means for performing said read, independent of any access on said second bus, whenever it is determined that said first bus access is a read.

21. An input/output controller as set forth in claim 20 further comprising means for performing a write, independent of any access on said second bus, whenever it is determined that said access is not a read.

22. An input/output controller as set forth in claim 21 wherein said means for performing said read further comprises:

(a) means, coupled to said first bus, for immediately transferring the contents of said pack/funnel register to said first bus whenever said first bus access is a read;

(b) buffer means, coupled to said first bus, for buffering the address of the first bus access;

(c) means, coupled to said buffer means, for translating said input address into a translated address; and

(d) means, coupled to said second bus, for performing a second bus read using said translated address and for storing the data read off said second bus in said pack/funnel register.

23. An input/output controller as set forth in claim 22 further comprising means, coupled to said pack/funnel register, for obtaining packed data from said packing and funneling means for storage in said pack/funnel register.

24. An input/output controller as set forth in claim 23 further comprising means for inhibiting a subsequent access to a given input/output port means via said first bus while said given input/output port means performs a read ahead/write behind operation.

25. An input/output controller as set forth in claim 24 wherein said means for performing said write further comprises:

(a) means, coupled to said first bus, for storing data being transferred from said first bus to said second bus, via said input/output port means, in said pack/funnel register whenever said input/output port means is accessed by said first bus to perform a write;

(b) buffer means, coupled to said first bus, for buffering the address of the first bus access;

(c) means, coupled to said buffer means, for translating said input address into a translated address; and

(d) means, coupled to said second bus, for performing a second bus write using said translated address and the data stored in said pack/funnel register.

26. An input/output controller as set forth in claim 25 further comprising means, coupled to said pack/funnel register, enabling data to be funneled from said pack/funnel register to said second bus via said packing and funneling means.

27. An input/output controller as set forth in claim 26 further comprising means for inhibiting a subsequent access to a given input/output port means via said first bus while said given input/output port means perform a read ahead/write behind operation.

28. An input/output controller as set forth in claim 3 further comprising means for performing read ahead and write behind operations in parallel wherein a first one of said plurality of input/output port means is utilized to perform said read ahead function while a second one of said plurality of input/output port means is used to perform the write behind function in parallel.

29. An input/output controller as set forth in claim 2 wherein said packing and funneling means further comprises:

(a) means for packing data on a transfer from said second bus to said first bus, including means for converting a number of byte and half word transfers on said second bus to a smaller number of half words and word transfers on said first bus; and

(b) means for buffering data being packed, by said means for packing, in order to facilitate full word transfers of packed data to said first bus.

30. An input/output controller as set forth in claim 2 wherein said packing and funneling means further comprises:

(a) means for funneling data on a transfer from said first bus to said second bus, including means for converting a number of word and half word transfers on said first bus to a larger number of half word and byte transfers on said second bus; and

(b) means for buffering data being funneled, by said means for funneling, in order to enable said means for funneling to extract half words and bytes of buffered data one at a time for transfer to said second bus.

31. An input/output controller as set forth in claim 1 suitable for transferring data between two synchronous buses.

32. An input/output controller as set forth in claim 1 suitable for transferring data between two asynchronous buses.

33. An input/output controller as set forth in claim 1 having a test mode of operation which allows the controller outputs to be driven for diagnostic purposes.

34. An input/output controller as set forth in claim 1 which is capable of processing I/O in parallel with at least one other input/output controller, to which it is connected, in a master/slave relationship.

35. A method for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU"), is attached, and a second bus to which a second set of relatively lower performance devices is attached, comprising the steps of:

(a) transferring data between said first bus and said second bus utilizing control means, including at least one address mapped input/output port means, coupled to said buses, wherein said step of transferring data includes the steps of determining if a first bus address supplied to said input/output port means by said first bus is within a preselected port means address space and translating said first bus address supplied to said input/output port means to a second bus address to be output to said second bus from the input/output port means; and

(b) decoupling the operation of said input/output port means with said controller means from program execution by said CPU to thereby prevent the performance of said first set of devices from being effected by the comparatively lower performance of said second set of devices when transferring data between said first and second bus via said control means.

36. A method as set forth in claim 35 further comprising the step of packing data being transferred from said second bus to said first bus to accommodate variable width data transfers.

37. A method as set forth in claim 36 further comprising the step of funneling data being transferred from said first bus to said second bus to accommodate variable width data transfers.

38. A method as set forth in claim 35 further comprising the step of multiplexing address signals and data signals being transferred to said second bus by said controller means.

39. A method as set forth in claim 35 further comprising the step of prioritizing accesses to said input/output port means whenever said input/output port means includes a plurality of input/output port means.

40. A method as set forth in claim 35 further comprising the step of checking parity for both data and address transfers.

41. A method as set forth in claim 35 further comprising the steps of controlling and maintaining the status of said input/output port means utilizing a set of internal registers located in said controller means.

42. A method as set forth in claim 35 wherein said step of decoupling further comprises the step of performing overlapped I/O.

43. A method as set forth in claim 35 wherein said decoupling is accomplished via performing overlapped input/output.

44. A method as set forth in claim 35 wherein said step of translating is performed by masking out a preselected number of high order bits from the first bus address and replacing said bits with the same number of high order bits of a second bus address.

45. A method as set forth in claim 43 wherein said step of decoupling further comprises the step of buffering data being transferring by said input/output port means to and from said second bus.

46. A method as set forth in claim 45 wherein said performing overlapped input/output further comprises the steps of:

(a) determining if said input/output port means is enabled to perform a read ahead/write behind operation instead of direct read/write operation; and

(b) responding immediately to an access request on said first bus whenever said input/output port means is enabled to perform a read ahead/write behind operation even though an access to said input/output port means by said second bus may be in progress.

47. A data transfer controller as set forth in claim 46 wherein said step of responding further comprises the steps of:

(a) latching an address of said first bus access;

(b) determining if said first bus access is a read; and

(c) performing said read, independent of any access on said second bus, whenever it is determined that said first bus access is a read.

48. A method as set forth in claim 47 further comprising the step of performing a write, independent of any access on said second bus, whenever it is determined that said access is not a read.

49. A method as set forth in claim 48 wherein said step of performing said read further comprises the steps of:

(a) transferring packed data, stored in said input/output port means, to said first bus whenever said first bus access is a read;

(b) buffering the address of the first bus access;

(c) translating said address to a corresponding second bus address;

(d) reading data off said second bus using said translated address; and

(e) storing data read off said second bus in said input/output port means.

50. A method as set forth in claim 49 further comprising the step of inhibiting a subsequent access to said input/output port means via said first bus while said input/output port means performs a read ahead/write behind operation.

51. A data transfer controller as set forth in claim 50 wherein said step of performing said write further comprises the steps of:

(a) storing data being transferred from said first bus to said second bus in said input/output port means whenever said input/output port means is accessed by an access request on said first bus to perform a write;

(b) buffering the address of the first bus access;

(c) translating said input address to a corresponding second bus address; and

(d) performing a write to said second bus using said translated address and the data stored in said input/output port means.

52. A method as set forth in claim 51 further comprising the step of funneling data from said input/output port means to said second bus via a packing and funneling means.

53. A method as set forth in claim 52 further comprising the step of inhibiting a subsequent access to a given input/output port means via said first bus while said given input/output port means performs a read ahead/write behind operation.

54. A method as set forth in claim 43 further comprising the step of performing read ahead and write behind operations in parallel wherein a plurality of input/output port means are provided and a first one of said input/output port means is utilized to perform said read ahead function while a second one of said input/output port means is used to perform the write behind function in parallel.

55. A method as set forth in claim 35 further comprising the steps of:

(a) packing data on a transfer from said second bus wherein said step of packing further includes the step of converting a number of byte and half word transfers on said second bus to a smaller number of half words and word transfers on said first bus; and

(b) buffering data being packed in order to facilitate full word transfers of packed data to said first bus.

56. A method as set forth in claim 35 further comprising the step of funneling data on a transfer from said first bus to said second bus wherein said step of funneling further includes the step of converting a number of word and half word transfers on said first bus to a larger number of half word and byte transfers on said second bus.

57. A method as set forth in claim 56 wherein said step of converting further comprises the steps of:

(a) buffering data being funneled; and

(b) extracting half words and bytes of buffered data, one at a time, for transfer to said second bus.