Sample-and-hold digital phase-locked loop for ask signals
First Claim
1. In a communication channel between an implanted device and a non-implanted device wherein an amplitude shift keyed (ASK) data signal is generated in one and received in the other of said implanted and non-implanted devices, a first binary state being indicated within said generated ASK data signal by the presence of a carrier signal, and a second binary state being indicated within said generated ASK data signal by the absence of said carrier signal, said generated ASK data signal comprising a data stream of binary bits, where each binary bit comprises a prescribed number of periods of said carrier signal during which said generated ASK data signal assumes either said first or second binary state, demodulation apparatus for demodulating said received ASK data signal comprising:
- means for generating a clock signal that is phase-locked with the carrier signal of said received ASK data signal when said carrier signal is present within said received ASK data signal, and that is phase-locked to the carrier signal that was most recently present within said received ASK data signal when said carrier signal is absent from said received ASK data signal; and
decision means synchronized with said clock signal for;
(1) determining whether said received ASK data signal indicates a first binary state, and if so for how many periods of said clock signal said first binary state continues, and (2) determining whether said received ASK data signal indicates a second binary sate, and if so for how many periods of said clock signal said second binary state continues;
whereby said data stream of binary bits within said generated ASK data signal can be recreated from said received ASK data signal by said demodulation apparatus.
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Accused Products
Abstract
A digital phase-locked looped generates a clock signal synchronized with a carrier signal modulated by amplitude shift keying (ASK). During periods when no carrier signal is present, the generated clock signal coasts at the frequency of the carrier signal most recently present, rather than trying to phase-lock on noise. A binary controlled digital oscillator generates the clock signal. A phase detector determines the difference between the phase of the carrier signal, when present, and the local clock signal. When the average amplitude of the carrier signal exceeds a prescribed threshold level, the phase detector output is sampled and passed to an integrator circuit, where the phase difference is integrated. The output of the integrator circuit is applied to a pulse generator, causing the pulse generator'"'"'s duty cycle to change proportionally. In turn, the pulses are applied to the binary controlled digital oscillator, causing the frequency of the local clock signal to shift in a direction that minimizes the phase error between the local clock signal and the carrier signal. When the average amplitude of the carrier signal is less than the prescribed threshold level, the phase detector output is not smapled. In such case, the output of the integrator circuit remains at the value obtained from the most recent prior phase detector sample.
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Citations
26 Claims
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1. In a communication channel between an implanted device and a non-implanted device wherein an amplitude shift keyed (ASK) data signal is generated in one and received in the other of said implanted and non-implanted devices, a first binary state being indicated within said generated ASK data signal by the presence of a carrier signal, and a second binary state being indicated within said generated ASK data signal by the absence of said carrier signal, said generated ASK data signal comprising a data stream of binary bits, where each binary bit comprises a prescribed number of periods of said carrier signal during which said generated ASK data signal assumes either said first or second binary state, demodulation apparatus for demodulating said received ASK data signal comprising:
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means for generating a clock signal that is phase-locked with the carrier signal of said received ASK data signal when said carrier signal is present within said received ASK data signal, and that is phase-locked to the carrier signal that was most recently present within said received ASK data signal when said carrier signal is absent from said received ASK data signal; and decision means synchronized with said clock signal for;
(1) determining whether said received ASK data signal indicates a first binary state, and if so for how many periods of said clock signal said first binary state continues, and (2) determining whether said received ASK data signal indicates a second binary sate, and if so for how many periods of said clock signal said second binary state continues;whereby said data stream of binary bits within said generated ASK data signal can be recreated from said received ASK data signal by said demodulation apparatus. - View Dependent Claims (2, 3, 4, 5, 6)
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7. Apparatus for generating a clock signal that is phase-locked with an amplitude modulated (AM) carrier signal, and apparatus comprising:
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means for generating a lock clock signal that has a frequency approximately equal to the frequency of said carrier signal, the frequency of said local clock signal being adjustable as controlled by a control signal; phase detector means for detecting the phase error between said carrier signal and said local clock signal; means for determining an average amplitude of said AM carrier signal and comparing said average amplitude to a prescribed value; sampling means for sampling the phase error detected by said phase detector means at least once during each period of said carrier signal only when the average amplitude of said AM carrier signal exceeds said prescribed value, whereby the phase error is not sampled when the average amplitude of said AM carrier signal is less than said prescribed value; integrating means for integrating the most recent sampled phase error obtained from said sampling means and for holding the resulting integrated sampled phase error until said sampling means again samples the phase error between said input signal and said clock signal, and output signal of said integrating means thereby comprising the integral of the most recent sampled phase error presented to the input of said integrating means; and means responsive to said output signal of said integrating means for generating said control signal, said control signal being applied to said local clock signal generation means to adjust the frequency thereof in a direction that minimizes the phase error between said local clock signal and said AM carrier signal. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A sample-and-hold digital phase-locked circuit for providing a local clock signal that is phase-locked to a carrier signal included within an amplitude shift keying (ASK) input signal, comprising:
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binary controlled digital oscillator means for generating said local clock signal; pulse generator means for generating a binary signal that controls said binary controlled digital oscillator as a function of a first input signal; phase detector means for measuring the phase error between said local clock signal and said input ASK signal; threshold means for determining an average amplitude of the carrier signal within said ASK input signal and comparing said average amplitude to a prescribed threshold; sampling means for sampling the phase error measured by said phase detector means at least once during each cycle of said local clock signal when the average amplitude of said carrier signal exceeds said prescribed threshold; and integrator means for integrating said sampled phase error from said sampling means, said integrated sampled phase error obtained from said integrator means comprising said first input signal applied to said pulse generator, said first input signal being applied to said pulse generator until said sampling means provides a new sample of the phase error to said integrator means.
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21. A method for extracting a clock signal that is phase-locked with an input signal modulated by amplitude shift keying (ASK) comprising the steps of:
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(a) generating a local clock signal having a frequency that varies as a function of a control signal; (b) detecting the phase difference between the ASK input signal and the local clock signal; (c) generating an error signal as a function of the phase difference detected in step (b); (d) comparing the amplitude of the ASK input signal with a prescribed threshold value; (e) sampling said error signal only when the amplitude of the ASK input signal exceeds said prescribed threshold value; (f) integrating said sampled error signal; (g) generating said control signal as a function of the integrated sampled error signal as a step (f) and maintaining the value of said control signal at a substantially constant value until the error signal is again sampled; and
(h) adjusting the frequency of said local clock signal as a function of the value of said control signal. - View Dependent Claims (22, 23, 24, 25, 26)
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Specification