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Sample-and-hold digital phase-locked loop for ask signals

  • US 4,947,407 A
  • Filed: 08/08/1989
  • Issued: 08/07/1990
  • Est. Priority Date: 08/08/1989
  • Status: Expired due to Term
First Claim
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1. In a communication channel between an implanted device and a non-implanted device wherein an amplitude shift keyed (ASK) data signal is generated in one and received in the other of said implanted and non-implanted devices, a first binary state being indicated within said generated ASK data signal by the presence of a carrier signal, and a second binary state being indicated within said generated ASK data signal by the absence of said carrier signal, said generated ASK data signal comprising a data stream of binary bits, where each binary bit comprises a prescribed number of periods of said carrier signal during which said generated ASK data signal assumes either said first or second binary state, demodulation apparatus for demodulating said received ASK data signal comprising:

  • means for generating a clock signal that is phase-locked with the carrier signal of said received ASK data signal when said carrier signal is present within said received ASK data signal, and that is phase-locked to the carrier signal that was most recently present within said received ASK data signal when said carrier signal is absent from said received ASK data signal; and

    decision means synchronized with said clock signal for;

    (1) determining whether said received ASK data signal indicates a first binary state, and if so for how many periods of said clock signal said first binary state continues, and (2) determining whether said received ASK data signal indicates a second binary sate, and if so for how many periods of said clock signal said second binary state continues;

    whereby said data stream of binary bits within said generated ASK data signal can be recreated from said received ASK data signal by said demodulation apparatus.

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