Echo measurement arrangement

• US 4,947,425 A
• Filed: 10/27/1989
• Issued: 08/07/1990
• Est. Priority Date: 10/27/1989
• Status: Expired due to Term

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.), Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: AT&T, Inc.
• Inventors: Sultana, George, Schmidt, Barnet M., Grizmala, Fredrick
• Primary Examiner(s): Ng, Jin F.
• Assistant Examiner(s): Augustus, Jhancy
• Application Number:
  US07/428,081
• Time in Patent Office: 284 Days
• Field of Search: 379/406, 379/410, 379/411, 370/32, 370/32.1
• US Class Current: 379/406.09
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04B 3/466 Testing attenuation in combination with at least one of group delay and phase shift

Abstract

A digital signal processor is provided with the facility to range and converge on each of a plurality of echoes occurring at respective locations along a communications line. Specifically, the digital signal processor is arranged to adaptively process samples of a signal that has been transmitted to the communications line correlated with samples of a signal that have been received from the communications line. In the processing of the samples, the digital signal processor separates and measures the magnitude of each echo that it converges on, beginning with a so-called near-end echo. In addition, the digital signal processor calculates the propagation delay of each echo that it converges on using the number of sampling intervals that have been processed in order to position the processor on the dispersion of that echo.

Claims

1. Apparatus for ranging and converging on at least one of a plurality of echoes occurring at respective locations along a communications line comprising

means for storing in a memory samples of a signal that is being transmitted to said communications line and samples of a signal that is being simultaneously received from said communications line,

at least one filtering means having respective coefficients for filtering overlapping sequences of said stored samples of said transmitted signal into a plurality of filtered signals, said one filtering means including means for changing the values of said respective coefficients as a function of each of said filtered signals and respective signals representative of respective ones of said stored received signal samples and for freezing the values of said coefficients when they reach respective final values as an indication that said one filtering means has converged on said at least one echo, and

means for determining the propagation delay associated with said at least one echo as a function of the effective number of said transmitted signal samples that are filtered up to the point at which said coefficients reach their respective final values.

2. The apparatus set forth in claim 1 further comprising means operative when said at least one filtering means converges on said at least one echo for finely tuning said at least one filtering means so that it covers the dispersion of said at least one echo.

3. The apparatus set forth in claim 1 wherein said at least one echo is associated with a respective echo path loss and wherein said apparatus further comprises means for determining said echo path loss as a function of the final values of said coefficients.

4. A filter circuit for ranging and converging on each of a plurality of echoes occurring at respective locations along a communications line comprising

means for storing in a memory samples of a signal that is being transmitted to said communications line and samples of a signal that is being simultaneously received from said communications line, and

a plurality of filtering means each having a respective group of filter coefficients, each of said filtering means being arranged to generate a filtered signal by sequentially and iteratively filtering respective overlapping sequences of said transmitted signal samples supplied to its input, a first one of said filtering means receiving at another input a respective sequence of said received signal samples and other ones of said filtering means each receiving at its other input an error signal outputted by a respective preceding one of said filtering means, said first one of said filtering means generating its error signal as a function of the value of its respective filtered signal and a respective one of said received signal samples and each of said other ones of said filtering means generating its error signal as a function of the value of its respective filtered signal and the value of the error signal that it receives at its other input, each of said filtering means converging on a respective one of said echoes by changing the values of its respective coefficients as a function of the current value of the error signal that it generates and freezing said values when the value of said error signal that it generates reaches a minimum.

5. The filter circuit set forth in claim 4 further comprising means operative when each of said plurality of filtering means has converged on its respective one of said echoes for arranging said plurality of filtering means to operate in a true cascade mode by causing the error signal generated by a last one of said plurality of means to be supplied to said first one of said plurality of filtering means and by causing each of said plurality of filtering means to re-converge on their respective ones of said echoes by supplying to each of said plurality of filtering means the sequence of said transmitted signal samples last supplied to said last one of said plurality of filtering means and by supplying to said first one of said filtering means respective receive signal samples that are correlated in time with respective ones of the samples contained in said last supplied sequence.

6. The filter circuit set forth in claim 4 wherein each of said echoes is associated with a respective echo path loss and wherein said filter circuit further comprises means for determining the echo path loss associated with at least one of said echoes that a respective one of said plurality of filtering means has converged on as function of the final values of the coefficients associated with said one of said plurality of said filtering means.

7. The filter circuit set forth in claim 4 wherein said filter circuit is a digital signal processor.

8. The filter circuit set forth in claim 4 wherein each of said plurality of filtering means changes the values of its respective coefficients in accordance with a predetermined least-means-squares algorithm.

9. The filter circuit set forth in claim 4 wherein said other ones of said plurality of filtering means receive said transmitted signal samples via respective delay lines arranged as a cascade of delay lines.

10. A method for ranging and converging on at least one of a plurality of echoes occurring at respective locations along a communications line, said method comprising the steps of

storing in a memory samples of a signal that is being transmitted to said communications line and samples of a signal that is being simultaneously received from said communications line,

filtering overlapping sequences of said stored samples of said transmitted signal into a plurality of filtered signals using at least one filtering means having a plurality of respective coefficients,

changing the values of said respective coefficients as a function of each of said filtered signals and respective signals representative of respective ones of said stored received signal samples,

freezing the values of said coefficients when they reach respective final values as an indication that said one filtering mean has converged on said at least one echo, and

determining the propagation delay associated with said at least one echo as a function of the effective number of said transmitted signal samples that have been filtered up to the point at which said coefficients reach their respective final values.