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Method of manufacturing self-aligned conformal metallization of semiconductor wafer by selective metal deposition

  • US 4,948,755 A
  • Filed: 07/11/1989
  • Issued: 08/14/1990
  • Est. Priority Date: 10/08/1987
  • Status: Expired due to Term
First Claim
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1. A method for fabricating a semiconductor integrated circuit comprising the steps of providing a substrate, forming a first dielectric layer over an upper surface of said substrate, forming a contact hole in said first dielectric layer and extending to said upper surface of said substrate, selectively depositing a metal so as to fill said contact hole with said metal, forming a thin silicon layer overlying the remaining portion of said first dielectric layer and over said metal-filled contact hole, forming a second dielectric layer over said thin silicon layer, using said thin silicon layer as an etching stop, selectively removing portions of said second dielectric layer, thereby to form at lest one trench in said second dielectric layer overlying said metalfilled contact hole, and thereafter depositing a metal to fill said trench to substantially the upper surface of said second dielectric layer while at the same time consuming the portion of said thin silicon layer not protected by the remaining portion of said second dielectric layer, whereby said last-mentioned metal is in electrical contact with metal in said underlying contact hole and is substantially coplanar with the upper surface of said second dielectric layer.

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