Adjustment circuit and method for solid-state electricity meter

• US 4,949,029 A
• Filed: 07/15/1988
• Issued: 08/14/1990
• Est. Priority Date: 07/15/1988
• Status: Expired due to Term

• Current Assignee: Itron, Inc.
• Original Assignee: Schlumberger Industries Incorporated (SLB)
• Inventors: Cooper, David M., Khandaghabadi, Ferrokh
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US07/220,121
• Time in Patent Office: 760 Days
• Field of Search: 324/74, 324/130, 324/73 R, 324/158 R, 324/142, 364/571
• US Class Current: 324/74
• CPC Class Codes: G01R 1/203 Resistors used for electric measuring, e.g. decade resistors standards, resistors for comparators, series resistors, shunts resistors in general H01C; microwave or radiowave terminations H01P1/26; coupling devices H01R
• CPC Class Codes: G01R 35/04 of instruments for measuring time integral of power or current

Abstract

A calibration circuit for a solid state electricity meter comprises a plurality of resistors formed on an integrated circuit. The resistors are connected by an on-chip array of electrically controlled switches, such as MOSFETs, to signal processing circuitry driving the meter. The resistors establish variable voltage divider networks which compensate the meter for phase, gain and offset errors distributed in the signal processing circuitry. The values of the variable voltage divider network may be established automatically during testing of the meter, by a digital computer, or semi-automatically, by a technician, to establish the "on" and "off" states of the various transistors of the array.

Claims

1. An improved power measurement calibration system for an electricity meter of the type comprising signal processing circuitry for determining line energy usage parameters by making power line current and voltage measurements, and, in response, obtaining an output signal related to said energy parameters, wherein errors tend to be contained in said output signal as a result of gain, phase and offset errors distributed within said signal processing circuitry, said improvement comprising:

memory means for storing calibration data in accordance with a calibration for correcting one of said errors in said output signal;

a plurality of interconnected resistors;

a plurality of electrically controlled switches responsive to said calibration data stored in said memory means and interconnected with said plurality of resistors to form a variable voltage divider network having output voltage divider values which depend on the "on" and "off" states of said switches;

means for obtaining a signal output from said voltage divider network which is representative of the calibration represented by said calibration data; and

means for connecting said signal output from said variable voltage divider network to said signal processing circuitry for correcting one of said errors, thereby calibrating said circuitry.

2. The calibration system of claim 1, wherein said electrically controlled switches are comprised of transistor switches.

3. The calibration system of claim 2, wherein the state of each of said transistor switches is controlled by data stored in said memory means.

4. The calibration system of claim 1, wherein said plurality of resistors are connected in series with nodes therebetween and said plurality of switches are interconnected together and to said nodes whereby there is a single output from said switches which is connected to a particular one of said nodes.

5. The calibration system of claim 4 wherein the data stored in said memory means is representative of the particular node to which said single output of said switches is to be connected.

6. The calibration system of claim 1, further comprising computer means for programming said memory means to store in said memory data representative of said calibration data corresponding to the desired calibration required to correct at least one of said errors.

7. The calibration system of claim 6, including a serial-to-parallel interface means for interfacing a serial flow of said calibration data between said computer means and said memory means.

8. The calibration system of claim 7, wherein said serial-to-parallel interface means comprises a shift register.

9. The calibration system of claim 8, including multiplexer means for establishing a signal flow path from said switch means and, selectively, one of said shift register and said memory means.

10. The calibration system of claim 9, wherein said multiplexer means comprises means responsive to a control signal indicating an operation mode or a test mode of said meter for selecting said signal flow path.

11. The calibration system of claim 8, including means for reading the output of said multiplexer means to determine the status of said electrically controlled switches.

12. The calibration system of claim 9, further comprising decoder means for interfacing said multiplexer means and said electrically controlled switches.

13. The calibration system of claim 12, wherein said decoder means includes means for decoding a data word corresponding to said calibration data having the following format:

space="preserve" listing-type="tabular">______________________________________ bit # Contents ______________________________________ 0 Phase A Bal. Adj. (LSB) 1 " 2 " 3 " 4 " 5 Phase A Bal. Adj. (MSB) 6 Phase A Phase Adj. (LSB) 7 " 8 " 9 Phase A Phase Adj. (MSB) 10 Phase B Bal. Adj. (LSB) 11 " 12 " 13 " 14 " 15 Phase B Bal. Adj. (MSB) 16 Phase B Phase Adj. (LSB) 17 " 18 " 19 Phase B Phase Adj. (MSB) 20 Phase C Bal. Adj. (LSB) 21 " 22 " 23 " 24 " 25 Phase C Bal. Adj. (MSB) 26 Phase C Phase Adj. (LSB) 27 " 28 " 29 Phase C Phase Adj. (LSB) 30 Offset Adj. (LSB) 31 " 32 " 33 " 34 Offset Adj. (MSB) 35 Gain Adj. (LSB) 36 " 37 " 38 " 39 " 40 " 41 Gain Adj. (MSB) 42 Detent ______________________________________

14. The calibration system of claim 8, including command signal decoder means responsive to input command signals for selectively establishing read and write modes of operation of said shift register and said memory means.

15. The calibration system of claim 1, wherein said signal processing circuitry includes measurement means coupled to said power line for obtaining current and voltage measurement signals, multiplier means for multiplying together said current and voltage measurement signals to obtain an analog line energy parameter measurement signal, and converter means for converting said analog line energy parameter measurement signal to an output signal having a frequency related to the magnitude of said analog line energy parameter measurement signal.

16. The calibration system of claim 1, wherein said resistors are formed of polysilicon.

17. The calibration system of claim 16, wherein said plurality of interconnected resistors, said plurality of electrically controlled switches, said means for obtaining a signal output from said voltage divider network, and said means for connecting said signal output from said variable voltage divider network to said signal processing circuitry are all formed on a single monolithic integrated circuit.

18. The calibration system of claim 17, wherein said single monolithic integrated circuit includes more than one of each of said plurality of interconnected resistors, said plurality of electrically controlled switches, said means for obtaining a signal output from said voltage divider network, and said means for connecting said signal output from said variable voltage divider network to said signal processing circuitry, whereby more than one of said gain, offset, and phase errors may be simultaneously corrected by said single integrated circuit.

19. The calibration system of claim 18, wherein said single monolithic integrated circuit further comprises a non-volatile memory for storing said calibration data.

21. The calibration system of claim 15, wherein said converter means includes a reference potential source and said connection means includes means for connecting one of said voltage divider networks between said reference potential source and said converter means to provide a composite gain adjustment of said signal processing circuitry.

30. The calibration system of claim 6, wherein said computer means is external to said electricity meters, and further comprising means for connecting said computer means to said memory means for transmitting said calibration data to said memory means for storage therein.

31. The calibration system of claim 6, wherein said memory means comprises a non-volatile permanent memory and a second volatile memory, and further comprising:

means for providing said calibration data to said volatile memory,

means for utilizing said calibration data in said volatile memory for an iterative calibration operation with said computer means until final calibration data is obtained corresponding to a desired final calibration, and

means for transferring said final calibration data to said non-volatile memory for permanent storage.

32. The calibration system of claim 31, wherein said utilizing means comprises a mulitplexer means for establishing a signal flow path from said switch means and, selectively, one of said non-volatile memory of said volatile memory.

20. An improved power measurement calibration system for an electricity meter of the type comprising signal processing circuitry for determining line energy usage parameters by making power line current and voltage measurements, and in response, obtaining an output signal related to said energy parameters, wherein errors tend to be contained in said output signal as a result of phase errors distributed within said signal processing circuitry, said improvement comprising:

(a) an adjustable voltage divider network comprised of a plurality of interconnected resistors and a plurality of electrically controlled switches interconnected with said plurality of resistors to form a variable voltage divider network having an output terminal and a variable voltage divider ratio which depends on the "on" and "off" states of said switches, said adjustable voltage divider network and said switches being formed on a monolithic integrated circuit; and

(b) a low pass network comprised of a resistor in series with a capacitor, the resistor of said low pass network being connected in parallel with said adjustable voltage divider network, the value of said resistor being less than the overall resistance of said voltage divider network, whereby changes in the voltage divider ratio cause the phase of voltage measured between said output terminal of said voltage divider network and the terminal of the capacitor in said low pass network which is not connected to said resistor in said low pass filter to vary in proportion to said voltage divider ratio.

22. For an electricity meter including signal processing circuitry for obtaining line energy usage parameter measurements by making power line current and voltage measurements, and in response, obtaining an output signal related to said usage parameter, wherein registration errors tend to be contained in said output signal as a result of gain, phase and offset errors distributed within said signal processing circuitry, said meter including a power measurement calibration apparatus comprising an integrated circuit;

a plurality of resistors formed on said integrated circuit;

electrically controlled switch means comprising transistors formed on said integrated circuit, said transistors interconnected with said plurality of resistors to form variable voltage divider networks depending upon respective states of said transistors;

memory means formed on said integrated circuit for storing data corresponding to respective on and off states of said transistors;

means for coupling control signals from said memory means to said transistors; and

means for connecting said variable voltage divider networks to said signal processing circuitry, a calibration method, comprising the steps of;

measuring registration errors of said signal processing circuitry;

estimating an amount of calibration correction required at each of a plurality of calibration circuits of said signal processing circuitry depending upon measured values of said registration errors;

providing calibration data corresponding to said calibration correction to said memory means for storage therein, and

controlling on and off states of said transistors in accordance with said calibration data stored in said memory means to reduce said registration errors.

23. The calibration method of claim 22, wherein said memory means comprises non-volatile memory means.

24. The calibration method of claim 22, wherein the step of providing said calibration data comprises:

providing said calibration data to said memory means from a source external to said integrated circuit; and

thereafter enabling said memory means to provide said control signals to said transistors.

25. The calibration method of claim 24, wherein said source external to said integrated circuit comprises an external computer, a program for said calibration computer for measuring said registration errors and determining, in response thereto, said calibration data, and means for connecting said calibration to said integrated circuit.

26. The calibration method of claim 25, further comprising the step of reading said memory means with said calibration computer to ascertain the current calibration.

27. The calibration method of claim 25, wherein said memory means comprises a non-volatile permanent memory and a second volatile memory, and further comprising the steps of providing said calibration data to said volatile memory, iteratively repeating the steps of measuring said registration errors, estimating said calibration correction, providing said calibration data to said volatile memory, and controlling said transistors in accordance with said calibration data to reduce said registration errors until said registration errors are within an acceptable tolerance and thereafter transferring a final calibration data to said non-volatile memory.

28. The calibration method of claim 27, wherein said method is preferred automatically by said calibration computer.

29. The calibration method of claim 27, wherein said method is preferred semi-automatically, with said calibration computer being utilized to provide said calibration data to said memory means.