Semiconductor integrated circuit device

• US 4,949,138 A
• Filed: 05/11/1989
• Issued: 08/14/1990
• Est. Priority Date: 10/27/1987
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Nishimura, Akitoshi
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US07/351,265
• Time in Patent Office: 460 Days
• Field of Search: 357/23.6, 357/41, 357/55
• US Class Current: 257/296
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A semiconductor IC device comprising a memory cell wherein a word line is buried in a groove formed in a semiconductor layer, a transfer gate transistor is constructed by the word line and a side area thereof, and on the surface of the semiconductor layer there is formed a capacitor having one electrode being a source or drain region of the transfer gate transistor and a dielectric film contacting with the electrode.

Claims

1. A semiconductor integrated circuit device comprising:

a semiconductor body having a top surface, said semiconductor body having a plurality of vertically elongated grooves provided therein opening onto the top surface thereof;

said semiconductor body including a lower semiconductor portion of one conductivity type and an upper semiconductor portion of the other conductivity type;

said plurality of vertically elongated grooves extending into said lower semiconductor portion of one conductivity type;

a plurality of regions of said one conductivity type provided in said upper semiconductor portion of the other conductivity type and opening onto the top surface of said semiconductor body, said plurality of regions being arranged in groups defining respective rows of said regions of said one conductivity type;

an insulation lining disposed in each of said grooves and covering the groove-defining surfaces of said semiconductor body;

a conductive material filling each of said grooves and being insulated from said semiconductor body by said insulation lining in said grooves;

an insulation layer disposed on said top surface of said semiconductor body and including spaced apart insulation portions of increased thickness, the remaining portions of said insulation layer being relatively thin in relation to said insulation portions of increased thickness;

each of said insulation portions of increased thickness extending above the upper surface and below the lower surface of said relatively thin remaining portions of said insulation layer, each of said insulation portions of increased thickness further being interposed between adjacent regions of said one conductivity type provided in said upper semiconductor portion of the other conductivity type to electrically isolate adjacent ones of said regions of said one conductivity type from each other and overlying said conductive material filling each of said grooves;

said relatively thin remaining portions of said insulation layer overlying said plurality of regions of said one conductivity type provided in said upper semiconductor portion of the other conductivity type and respectively extending between adjacent insulation portions of increased thickness;

a plurality of strips of conductive material overlying said insulation layer in registration with respective rows of said regions of said one conductivity type;

said semiconductor body, said conductive material filling each of said grooves in said semiconductor body, said insulation layer and said plurality of strips of conductive material cooperating to define a plurality of memory cells each comprising a transfer gate transistor and a capacitor;

the transistor of each memory cell being vertically arranged along the conductive material filling a respective groove and including one of said regions of said one conductivity type as a source region, the upper semiconductor portion of said other conductivity type as a channel region, and the lower semiconductor portion of said one conductivity type as a drain region, with said conductive material filling said groove being a transfer gate;

the capacitor of each memory cell including said one region of said one conductivity type forming the source region of said transistor as a first electrode, a respective one of said plurality of strips of conductive material in registration with the row containing said one region of said one conductivity type as a second electrode, and a respective relatively thin portion of said insulation layer as the dielectric layer between said first and second electrodes; and

said conductive material filling each of said grooves in said semiconductor body serving as respective word lines and said plurality of strips of conductive material serving as bit lines for the plurality of memory cells.

2. A semiconductor integrated circuit device as set forth in claim 1, wherein said lower semiconductor portion of said semiconductor body is a semiconductor substrate of one conductivity type, and said upper semiconductor portion of said semiconductor body is an epitaxial layer of semiconductor material of the other conductivity type disposed on said semiconductor substrate of one conductivity type and defining the top surface of said semiconductor body;

said plurality of vertically elongated grooves extending into said semiconductor substrate of one conductivity type and opening onto the top surface of said semiconductor body as provided by said epitaxial semiconductor layer of the other conductivity type.

3. A semiconductor integrated circuit device as set forth in claim 1, wherein each respective relatively thin portion of said insulation layer defining the dielectric layer between said first and second electrodes of the capacitor of each of said plurality of memory cells is of substantially uniform thickness.

4. A semiconductor integrated circuit device as set forth in claim 3, wherein each of the vertically elongated grooves included in said plurality of vertically elongated grooves is defined by substantially vertical side wall surfaces of said semiconductor body.

5. A semiconductor integrated circuit device as set forth in claim 4, wherein the conductive material filling each of said grooves is polysilicon so as to define said word lines as polysilicon conductors.

6. A semiconductor integrated circuit device as set forth in claim 5, wherein said plurality of strips of conductive material are polysilicon so as to define said bit lines as polysilicon conductors.

7. A semiconductor integrated circuit device as set forth in claim 2, wherein said semiconductor substrate of said semiconductor body is silicon material of one conductivity type, said epitaxial semiconductor layer disposed on said silicon substrate is epitaxial silicon of the other conductivity type, said insulation lining and said insulation layer are silicon oxide, and said word lines and said bit lines are polysilicon conductors.

8. A semiconductor integrated circuit device as set forth in claim 1, wherein the corresponding source regions of said vertically arranged transistors included in each memory cell underlying adjacent bit lines are disposed in staggered relation with respect to each other.