Semiconductor integrated circuit device made by a standard-cell system and method for manufacture of same

• US 4,949,275 A
• Filed: 07/08/1985
• Issued: 08/14/1990
• Est. Priority Date: 07/13/1984
• Status: Expired due to Term

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Nonaka, Terumoto
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Trans, V. N.
• Application Number:
  US06/752,934
• Time in Patent Office: 1,863 Days
• Field of Search: 364/489, 364/490, 364/491, 364/200, 364/900, 364/525, 364/488, 307/453, 307/219, 307/465, 307/441, 307/442, 357/51, 357/68
• US Class Current: 326/101
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits

Abstract

A semiconductor integrated circuit device comprises a semiconductor chip with a plurality of standard cells formed thereon. Each of said standard cells consists of at least one type of standard cell which is selected from among a plural types of standard cells which are pre-registered in a standard cell library retained by a computer. The placement and routing pattern of said standard cells on said semiconductor chip are designed automatically by a computer system. In relation to at least one of said standard cells, at least one basic cell for general-purpose logical gate is formed on said semiconductor chip to deal with design modification of the device.

Claims

1. A semiconductor integrated circuit device comprising:

a semiconductor chip with a plurality of standard cells formed thereon, wherein the standard cells comprise an initial circuit, and wherein each of said standard cells is selected from among plural types of standard cells which are pre-registered in a standard cell library retained by a computer, the placement pattern of said standard cells on said semiconductor chip being designed automatically by a computer system in accordance with an initial circuit design which includes the standard cells as constituent elements thereof and which includes the initial design of the electrical interconnection pattern of the standard cells; and

at least one basic cell comprised of the circuit elements for at least one general-purpose logical gate formed on said semiconductor chip in addition to the standard cells, wherein at least one of the basic cells is electrically connected to said initial circuit to form a modified circuit design different from the initial design.

2. A semiconductor integrated circuit device according to claim 1, wherein said at least one basic cell is designed to be placed in an empty region of said semiconductor chip after designing the layout of said standard cells.

3. A semiconductor integrated circuit device according to claim 1, wherein said at least one basic cell is designed to be placed on said semiconductor chip at the same time of designing the placement of said standard cells.

4. A semiconductor integrated circuit device according to claim 1, wherein wiring and routing in association with said at least one basic cell is carried out after the routing in association with said standard cells.

5. A semiconductor integrated circuit device as in claim 1, wherein a plurality of basic cells are formed on the semiconductor chip, each basic cell comprising circuit elements for at least one general purpose gate, and wherein at least one of the plural basic cells includes circuit elements not electrically connected to any other circuit elements.

6. A semiconductor integrated circuit device as in claim 5, wherein each basic cell includes as a circuit element one transistor, diode or resistor.

7. A semiconductor integrated circuit device comprising:

a substrate;

a plurality of standard cells formed on the substrate and comprising an initial circuit in accordance with an initial circuit design which includes the placement and the electrical interconnection of the standard cells, each standard cell made up of a predetermined arrangement of circuit elements to provide a particular logic function, wherein each standard cell is selected from a group of different types of standard cells which are stored in a standard cell library;

a plurality of basic cells formed on the substrate in addition to the standard cells, each basic cell comprised of the circuit elements for at least one logic gate; and

interconnections between at least one of the standard cells and at least one of the plurality of basic cells to form a modified circuit design different from the initial circuit design.

8. A semiconductor integrated circuit device as in claim 7, wherein less than all of the basic cells are electrically interconnected with the standard cells.

9. A semiconductor integrated circuit device as in claim 8, wherein each basic cell includes as a circuit element one transistor, resistor or diode.

10. A semiconductor integrated circuit device comprising:

a semiconductor chip including a plurality of standard cells constituting an initial circuit, each standard cell providing a predetermined logic function and being selected from a library of different types of standard cells which is stored in a computer, the layout of the standard cells being designed automatically by a computer system in accordance with an initial circuit design of which the standard cells are constituent elements and which includes the design of the interconnection of the standard cells; and

a plurality of basic cells formed on the chip in addition to the standard cells, each basic cell including the circuit elements for providing a logic function, wherein less than all of the basic cells are electrically connected to the standard cells of the initial circuit, thereby to form a modified circuit design.

11. A semiconductor integrated circuit device as in claim 10, wherein the circuit elements of the basic cells not electrically connected to the standard cells are also not electrically connected to any other circuit elements.

12. A semiconductor integrated circuit device as in claim 11, wherein each basic cell includes as a circuit element one transistor, resistor or diode.

13. A semiconductor integrated circuit device as in claim 10, wherein none of the basic cells are electrically connected to any of the standard cells.

14. A method for forming an integrated circuit chip comprising the steps of:

designing a layout for an integrated circuit chip by (a) designing an initial circuit by selecting a plurality of standard cells, each of which provides a predetermined logic function, from a library of standard cells and determining location and interconnection of the standard cells under computer control and (b) providing at least one basic cell, which includes the circuit elements for providing a logic function and which is not connected to the initial circuit;

producing an integrated circuit chip in accordance with said design;

evaluating the produced chip;

designing a new interconnection pattern to form a modified circuit different from the initial circuit based on the same layout of the standard cells and the basic cells as in the initial circuit and having the circuit elements of at least one basic cell electrically interconnected to a standard cell; and

producing integrated circuits in accordance with the modified design.

15. A method as in claim 14, wherein the circuit elements of the at least one electrically interconnected basic cell form a logic gate.

16. A semiconductor integrated circuit device comprising:

a semiconductor chip with a plurality of standard cells formed thereon, wherein the standard cells comprise an initial circuit, and wherein each of said standard cells is selected from among plural types of standard cells which are pre-registered in a standard cell library retained by a computer, the placement pattern of said standard cells on said semiconductor chip being designed automatically by a computer system in accordance with an initial circuit design which includes the standard cells as constituent elements thereof and which includes the initial design of the electrical interconnection pattern of the standard cells; and

a plurality of basic cells in addition to the standard cells, each basic cell being comprised of the circuit elements for at least one general-purpose logical gate, wherein the basic cells are formed on said semiconductor chip in addition to the standard cells, and wherein less than all of the basic cells are electrically connected to said initial circuit to thereby form a modified circuit different from the initial circuit design.

17. A method for forming integrated circuits comprising the steps of:

designing a layout for an integrated circuit chip by (a) designing an initial circuit by selecting a plurality of standard cells from a library of standard cells (b) determining the locations and interconnections of the standard cells and (c) providing at least one basic cell in the layout of the integrated circuit which basic cell is not connected to the initial circuit;

producing an integrated circuit chip in accordance with said design, including the at least one unconnected basic cell and the electrically interconnected standard cells;

evaluating the produced design;

modifying the interconnections to form a modified circuit based on the same layout of the standard cells and the basic cells as in the initial circuit and having at least one basic cell electrically interconnected to a standard cell; and

producing integrated circuits in accordance with the modified design.

18. A method as in claim 17, wherein the at least one electrically interconnected basic cell includes circuit elements forming a logic gate.

19. A semiconductor integrated circuit device comprising:

a semiconductor chip having a plurality of standard cells formed thereon, wherein the standard cells constitute an initial circuit, and wherein each of said standard cells is selected from among plural types of standard cells which are pre-registered in a standard cell library;

first electrical interconnections between the standard cells;

a plurality of basic cells formed on said semiconductor chip in addition to the standard cells; and

second electrical interconnections between the standard cells and less than all of the basic cells, wherein the second electrical interconnections form a modified circuit different from the initial circuit.

20. A semiconductor integrated circuit device as in claim 19, wherein each of the basic cells includes circuit elements for forming a logic gate, the semiconductor integrated circuit device further comprising third electrical interconnections between the circuit elements of less than all of the basic cells, said third interconnections forming logic elements from the interconnected circuit elements.