Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs

• US 4,949,301 A
• Filed: 03/06/1986
• Issued: 08/14/1990
• Est. Priority Date: 03/06/1986
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Iyer, Venkatraman, Joshi, Sunil P.
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): Harrell, Robert B.
• Application Number:
  US06/836,936
• Time in Patent Office: 1,622 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 370/94
• US Class Current: 711/100
• CPC Class Codes: G06F 2205/064 Linked list, i.e. structure using pointers, e.g. allowing non-contiguous address segments in one logical buffer or dynamic buffer space allocation
• CPC Class Codes: G06F 2205/066 User-programmable number or size of buffers, i.e. number of separate buffers or their size can be allocated freely
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Abstract

A RAM buffer controller for managing the address input lines of a RAM buffer to simulate the operation of two FIFO'"'"'s therein. Apparatus is included for allowing random access by a node processor in a local area network node using the RAM buffer controller to manage "transmit and receive" FIFO'"'"'s to have random access to any address in the address space of the buffer without restriction to FIFO boundaries. Apparatus is also included for transmitting packets from said buffer organized into one or two linked lists. Further, apparatus is included for allowing independent initialization of any of the pointers in the RAM buffer controller which are not currently selected, and for allowing software requests for read or write access by the node processor. Further, apparatus and a method are utilized for recording status and length information at the end of a packet instead of in front thereof and for allowing any incoming packet to be flushed without saving status information or to be flushed while saving its status information.

Claims

1. An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;

second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;

third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;

wherein said first means stores a write address pointer and read address pointer for receiving packets to be stored in said memory and a read address pointer and a write address pointer for transmit packets to be retrieved from said memory for transmision, said receive packets and transmit packets being received from and/or sent to said accessing devices;

further comprising an initialization bus coupled to said first means, and fourth means coupled to said initialization bus and said first means for receiving and storing starting address pointers on said initialization bus and said initialization bus for allowing independent setting of any of said address pointers to a selected address, and said fourth means also for causing said starting address pointers to be stored in said first means at predetermined times, wherein said first means includes a plurality of registers for storing said address pointers including a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets where said first and second registers have inputs and outputs, and further comprising first and second multiplexers having outputs coupled respectively to said inputs of said first and second registers, each said multiplexer having a plurality of inputs wherein one input of said first multiplexer is coupled to said third means for receiving the incremented value of said write pointer for receive packets when said second means selects the write pointer for receive packets for output to said memory and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of each of said first and second multiplexers.

2. The apparatus of claim 1, further comprising fifth means coupled to said initialization bus for receiving and storing end addresses for said receive and transmit packets in said memory and sixth means coupled to said fifth means and to said second means for comparing the receive and transmit address pointers to the said end addresses for said receive and transmit packets, respectively, and for generating an end signal indicating whether either of said receive and transmit address pointers is equal or not equal to said end addresses for said receive and transmit packets, respectively.

3. An apparatus as defined in claim 2 further comprising a multiplexer having its output coupled to a data input of said first means and having an input coupled to an output of said fourth means for storing said starting address pointers and an input coupled to said initialization bus and having a control input and further comprising control means coupled to said control input and to said sixth means for receiving said end signal and for determining when the selected read pointer or write pointer has become equal to said end address and for causing said multiplexer to select the output of said fourth means such that the proper starting address pointer for the FIFO corresponding to the selected read or write pointer may be stored in said first means as the new value for the selected read or write pointer address.

4. An apparatus as defined in claim 3 further comprising full/empty comparison means coupled to said first means for comparing said read and write pointers for receive packets and generating a first signal indicating whether said pointers are equal and for comparing said read and write pointers for said transmit packets and generating a second signal indicating whether said pointers are equal.

5. An apparatus as defined in claim 4 further comprising means coupled to said full/empty comparison means for receiving said first and second signals and for determining which of said read and write pointers was incremented so as to cause the compared pointers to become equal for making a determination in the case of said first signal indicating the status of the receive FIFO whether that FIFO is full or empty and for making a determination in the case of said second signal indicating the status of the transmit FIFO whether that FIFO is full or empty.

6. An apparatus as defined in claim 2 wherein said fifth means includes means for allowing the end pointer addresses to be initialized or changed to any desired address within the address space of said memory.

7. An apparatus as defined in claim 3 further comprising a random access memory address register coupled to said initialization bus and wherein said control means ignores said end signal when said second means selects the output of said random access memory address register for output to said memory.

8. An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;

second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;

third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;

wherein said memory includes a first stack and a second stack and said third means is also for decrementing the selected address pointer, further comprising means coupled to said first means for independently initializing separate write and read pointers for said first stack and for initializing separate write and read pointers for said second stack and for controlling said third means to manage the incrementing and decrementing of said write and read pointers such that a last-in, first-out memory access operation in said memory may be performed, wherein said first means includes a plurality of registers for storing said address pointers including a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets where said first and second registers have inputs and outputs, and further comprising first and second multiplexers having outputs coupled respectively to said inputs of said first and second registers, each said multiplexer having a plurality of inputs wherein one input of said first multiplexer is coupled to said third means for receiving the incremented value of said write pointer for receive packets when said second means selects the write pointer for receive packets for output to said memory and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of each of said first and second multiplexers.

9. An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;

second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;

third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;

wherein said first means stores a write address pointer and read address pointer for receiving packets to be stored in said memory and at least two read address pointers and a write address pointer for transmit packets to be retrieved from said memory for transmission; and

wherein said first means includes a plurality of registers, each said register for storing one of said address pointers, one of said registers for storing the read address pointer for transmit packets, and further comprising linked list means, connected to said first means, for receiving and storing at least two separate and independent link pointers for at least two separate and independent linked lists as said at least two read address pointers for said transmit packets.

10. An apparatus as defined in claim 9 further comprising an initialization bus for carrying initial addresses for said pointers for transmit packets and a DBI bus for carrying linking addresses for storage in the registers storing the read pointer addresses for transmit packets and wherein said linked list means includes input multiplexer means having outputs coupled to the data inputs of said registers for storing read addresses for transmit packets and having inputs coupled to said initialization bus and having an input coupled to said DBI bus and having inputs coupled to said third means and having a control input, and further comprising control means coupled to said control input for causing said multiplexer to select an input coupled to said DBI bus for coupling to an output coupled to a read address pointer storage register for transmit packets during transmission of a packet organized as a first linked list in said memory such that linking addresses from said DBI bus will be loaded in the register storing the read pointer for transmit packets and, at other times, for causing said multiplexer to select an input coupled to said DBI bus for coupling to a read address pointer storage register for transmit packets during transmisssion of a packet organized as a second linked list independent of said first linked list.

11. An apparatus as defined in claim 10 further comprising a starting address register for storage a new link address pointing to the location in memory of a predetermined packet and having an input coupled to said initialization bus and having an output coupled at least to an input of the input multiplexer having its output coupled to the input of the register storing the read pointer for the transmit packets, said control means for receiving a signal INICLBN indicating that said predetermined packet should be sent, said control means for causing said input multiplexer to select the input coupled to the output of said starting address register when said INICLBN signal is received.

12. An apparatus as defined in claim 11 further comprising an end address register having an input and a second input multiplexer having an input coupled to the output of said register for storing the read address pointer for the transmit packets and having its output coupled to said input of said end address register and having a control input, and wherein said control means is also coupled to said control input of said second input multiplexer and wherein said control means is also for simultaneously causing said second input multiplexer to select said input coupled to the output of said register for storing the read address pointer for transmit packets simultaneously with the selection by said input multiplexer of its input coupled to the output of said starting address register upon receiving said INICLBN signal such that the link address is loaded in said register which is for storing the read pointer for transmit packets simultaneously with the loading of the current read pointer for transmit packets into the end address register.

13. An apparatus as defined in claim 9, wherein said first means includes a starting address register and an ending address register, said starting address register being coupled to an input of a first said read address pointer storage register for transmit packets, and said ending address register being coupled to an output of said first read address pointer storage register, and further comprising means for, causing the read address pointer stored in said read address pointer storage register to be stored in said ending address storage register and for causing an address stored in said starting address register to be stored in said first read address pointer storage register for transmit packets at a selected time.

14. An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;

second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;

third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;

wherein said first means comprises a plurality of registers for storing said address pointers and further comprises a plurality of multiplexers each having an output, with one said multiplexer output coupled to a data input of a respective one of said plurality of registers, and each said multiplexer having a plurality of inputs including first inputs and second inputs, and further comprising an initialization bus coupled to said first inputs and wherein said third means is coupled to said second inputs, where said plurality of registers includes a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets, where said first and second registers have inputs and outputs, and wherein said plurality of multiplexers includes first and second multiplexers having outputs coupled, respectively, to said inputs of said first and second registers, each of said first and second multiplexers having a plurality of inputs, wherein one input of said first multiplexer is coupled to said third means for receiving the incremented value of said write pointer for received packets for output to said memory, and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of said first and second multiplexers.

15. An apparatus as defined in claim 14 wherein one of said registers is a random access memory address register.

16. An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;

second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;

third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;

wherein said first means includes a plurality of registers for storing said address pointers including a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets where said first and second registers have inputs and outputs, and further comprising first and second multiplexers having outputs coupled respectively to said inputs of said first and second registers, each said multiplexer having a plurality of inputs wherein one input of said first multiplexer is coupled to said third means for receiving the incrmented value of said write pointer for receive packets when said second means selects the write pointer for receive packets for output to said memory and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of each of said first and second multiplexers.

17. An apparatus as defined in claim 16 wherein said first and second multiplexers also have control inputs and further comprising control means coupled to said control inputs and further comprising data path controller means coupled to said control means, said control means having a first input for receiving a FSHRCVP signal from said data path controller means indicating a packet or portion thereof received from one of said accessing devices is to be flushed and having a second input for receiving a BRCVPKT signal from said data path controller means indicating packet reception is beginning and having a third input for receiving DWRREQ signal from said data path controller means indicating that packet reception is occurring, said control means for causing said second multiplexer to select the input coupled to the output of said first register and for causing said first multiplexer to select the input coupled to said third means to cause said first register to load the write pointer for receive packets as incremented by said third means upon receiving said BRCVPKT signal and for causing said first multiplexer to continue to select said input coupled to said third means upon receiving said DWRREQ signal and for causing said first multiplexer to select the input coupled to the output of said second register and thereafter to cause said first multiplexer to select said input coupled to said third means upon receiving said FSHRCVP signal.

18. An apparatus as defined in claim 16 wherein said first and second multiplexers also have control inputs and further comprising control means coupled to said control inputs, and further comprising data path controller means coupled to said control means, said control means having a first input for receiving a FSHRCVP signal from said data path controller means indicating a packet or portion thereof received from one of said accessing devices is to flushed, and having a second input for receiving a BRCVPKT signal from said data path controller means indicating packet reception is beginning, and having a third input for receiving a DWRREQ signal from said data path controller means indicating that packet reception is occurring, and having a fourth input for receiving an ERCVPKT signal from said data path controller means indicating a packet has been successfully received, said control means for causing said second multiplexer to select the input coupled to the output of said first register to cause the then existing write pointer for receive packets to be saved in the second register and for causing said first multiplexer to select the input coupled to said third means to cause said first register to load the write pointer for receive packets as incremented by said third means upon receiving said BRCVPKT signal and for causing said first multiplexer to continue to select said input coupled to said third means upon receiving said DWRREQ signal such that the write pointer for receive packets is incremented on every clock cycle during packet reception and, upon receiving said ERCVPKT signal, for causing said first multiplexer to select the input coupled to the output of said second register and for causing said second multiplexer to select the input coupled to the output of said first register such that the contents of these two registers are exchanged, and for causing said second means to select the output of said first register for application to the address inputs of said memory, with said data path controller means also coupled to the data inputs of said memory for keeping track of the length of the received packet and its status and for writing this data into the location in memory pointed to by the current contents of said first register, said control means also for causing said first multiplexer to select the input coupled to the output of said second register after said status and length data is written so as to cause said first register to load the contents of said second register to restore the write pointer for receive packets to its state as it existed at the time of receiving said ERCVPKT signal, said data path controller means for writing predetermined bit in the memory location addressed by the contents of said first register and for subsequently causing said first multiplexer to select the input coupled to the output of said first register until the next BRCVPKT signal is received.

19. An apparatus as defined in claim 16 wherein said first and second multiplexers also have control inputs and further comprising control means coupled to said control inputs, and further comprising data path controller means coupled to said control means, said control means having a first input for receiving a FSHRCVP signal from said data path controller means indicating a packet or portion thereof received from one of said accessing devices is to be flushed, and having a second input for receiving a BRCVPKT signal from said data path controller means indicating packet reception is beginning, and having a third input for receiving a DWRREQ signal from said data path controller means indicating that packet reception is occurring, and having a fourth input for receiving an RCVABRT signal from said data path controller means indicating a packet that has been received or partially received is to be aborted but its status and length information is to be recorded, said control means for causing said second multiplexer to select the input coupled to the output of said first register to cause the then existing write pointer for receive packets to be saved in the second register and for causing said first multiplexer to select the input coupled to said third means to cause said first register to load the write pointer for receive packets as incremented by said third means upon receiving said BRCVPKT signal, and for causing said first multiplexer to continue to select said input coupled to said third means upon receiving said DWRREQ signal such that the write pointer for receive packets is incrmented on every clock cycle during packet reception and, upon receiving said RCVABRT signal, for causing said first multiplexer to select the input coupled to the output of said second register such that the contents of the second register is loaded in said first register, and for causing said second means to select the output of said first register for application to the address inputs of said memory, with said data path controller means also coupled to the data inputs of said memory for keeping track of the length of the received packet and its status and for writing this data into the location in memory pointed to by the current contents of said first register, said control means also for causing said first multiplexer to select the input coupled to the output of said third means after said status and length data is written so as to cause said first register to reload the current write pointer for receive packets as incremented by said third means, said data path controller for writing a predetermined bit in the memory location addressed by the contents of said first register after its contents have been incremented and for subsequently causing said first multiplexer to select the input coupled to the output of said first register until the next BRCVPKT signal is received.

20. An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;

second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;

third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;

further comprising arbitration means coupled to said second means and having a plurality of service request signal inputs from said accessing devices for receiving signals indicating that a particular pointer is desired to be selected, said arbitration means for arbitrating said request signals and selecting the currently asserted request with the highest priority;

wherein said first means includes a plurality of registers for storing said address pointers including a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets where said first and second registers have inputs and outputs, and further comprising first and second multiplexers having outputs coupled respectively to said inputs of said first and second registers, each said multiplexer having a plurality of inputs wherein one input of said first multiplexer is coupled to said third means for receiving the incremented value of said write pointer for receive packets when said second means selects the write pointer for receive packets for output to said memory and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of each of said first and second multiplexers.

21. An apparatus for controlling the address inputs of a memory, comprising:

first means for storing plurality of address pointers;

second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;

third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;

further comprising arbitration means coupled to said second means and having a plurality of service request signal inputs from said accessing devices for receiving signals indicating that a particular pointer is desired to be selected, said arbitration means for arbitrating said request signals and selecting the currently asserted request with the highest priority;

wherein said first means includes a plurality of registers for storing said address pointers including a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets where said first and second registers have inputs and outputs, and further comprising first and second multiplexers having outputs coupled respectively to said inputs of said first and second registers, each said multiplexer having a plurality of inputs wherein one input of said first multiplexer is coupled to said third means for receiving the incremented value of said write pointer for receive packets when said second means selects the write pointer for receive packets for output to said memory and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of each of said first and second multiplexers; and

further comprising a clock input of receiving a clock signal and wherein said second means has a control input and wherein said first means comprises a plurality of registers for storing predetermined ones of said pointer addresses, each register having an input and an output and a clock input for receiving said clock signal for causing the data at said input to be latched into said register and to be available for output on said output, and further comprising a plurality of multiplexers each having its output coupled to a said input of one of said registers and each having at least one input coupled to the output of the register to which the multiplexer has its output coupled, and wherein said third means has an output carrying the incremented value of the pointer selected by said second means, said output of said third means coupled to another input of each said multiplexer, and each said multiplexer having a control input, and further comprising a control means coupled to said control inputs of said multiplexers and to said arbitration means and to a control input of said second means for sensing which request signal has received priority and for causing said second means to select the appropriate one of said pointers in accordance with the result of the arbitration and for causing said multiplexer coupled to the input of the reigster whose pointer contents have been selected for output by said second means to select its input coupled to the output of said third means for a first clock cycle and for causing said multiplexer input coupled to the selected register to select the multiplexer input coupled to the output of the selected register during a second clock cycle.

22. The apparatus of claim 21, wherein said memory has address inputs and said control means also causes said arbitration means to perform its next arbitration for said incremented pointer to be selected during said second clock cycle during which the currently selected pointer is selected for output to said address inputs of said memory.

23. An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;

second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;

third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;

wherein said first means includes a plurality of registers for storing said pointers and further comprises an initialization bus coupled to an input of each register and wherein one of said registers is for storing a random access address pointer which can be set initially by said data on said initialization bus and will be incremented by said third means when said random access pointer is selected for output by said second means;

where said plurality of registers includes a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets, where said first and second registers have inputs and outputs, and further comprising first and second multiplexers having outputs coupled, respectively, to said inputs of said first and second registers, each of said first and second multiplexers having a plurality of inputs, wherein one input of said first multiplexer is coupled to said third means for receiving the incremented value of said write pointer for receive packets for output to said memory, and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of said first and second multiplexers.

24. An apparatus as defined in claim 23 further comprising arbitration means having a plurality of inputs for coupling to conductors carrying request signals and coupled to said second means for arbitrating any simultaneously asserted requests from said accessing devices and selecting the highest priority request and for causing said second means to provide said random access pointer register output as output to said memory.

25. An apparatus as defined in claim 24 further comprising means having an instruction bus input and coupled to said second means for decoding an instruction received at said instruction bus input.

26. An apparatus as defined in claim 23 further comprising instruction decoder means having an instruction bus input and coupled to said second means for decoding an instruction received at said instruction bus input.

27. An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;

second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;

third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;

wherein said first means includes a plurality of registers for storing said pointers and further comprises an initialization bus coupled to an input of each register and wherein one of said registers is for storing a random access address pointer which can be set initially by said data on said initialization bus and will be incremented by said third means when said random access pointer is selected for output by said second means;

further comprising instruction decoder means having an instruction bus input and coupled to said second means for decoding an instruction received at said instruction bus input; and

wherein said instruction decoder means is also coupled to said third means for stopping the third means from incrementing the selected pointer when a predetermined instruction is received.

28. An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;

second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;

third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;

further comprising an initialization bus and wherein said first means comprises a plurality of registers each having an input and further comprises a plurality of multiplexers, each said multiplexer having an output coupled to a respective one of said register inputs, each said multiplexer also having an input coupled to said third means for receiving the incremented value of the selected pointer and each said multiplexer also having an input coupled to said initialization bus;

where said plurality of registers includes a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets, where said first and second registers have inputs and outputs, and wherein said plurality of multiplexers includes first and second multiplexers having outputs coupled, respectively, to said inputs of said first and second registers, each of said first and second multiplexers having a plurality of inputs, wherein one input of said first multiplexer is coupled to said third means for receiving the incremented value of said write pointer for receive packets for output to said memory, and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of said first and second multiplexers.

29. An apparatus for controlling the address inputs of a memory, comprising:

first means for storing a plurality of address pointers;

second means coupled to said first means for selecting one of said address pointers and for outputting said selected address pointer to said memory;

third means coupled to said second means and to said first means for incrementing the selected address pointer and loading it back into said first means to replace the selected address pointer;

further comprising an initialization bus and wherein said first means comprises a plurality of registers each having an input and further comprises a plurality of input multiplexers, each said multiplexer having an output coupled to a respective one of said register inputs, and further comprising a source multiplexer having an input coupled to said initialization bus and having an input coupled to said third means and having an output, each said input multiplexer having an input coupled to said output of said source multiplexer;

where said plurality of registers includes a first register for storing a write pointer for receive packets and having an output coupled to said second means and a second register for storing a shadow write pointer for receive packets, where said first and second registers have inputs and outputs, and wherein said plurality of multiplexers includes first and second multiplexers having outputs coupled, respectively, to said inputs of said first and second registers, each of said first and second multiplexers having a plurality of inputs, wherein one input of said first multiplexer is coupled to said third means for receiving the incremented value of said write pointer for receive packets for output to said memory, and wherein the output of said second register is coupled to an input of each of said first and second multiplexers and wherein the output of said first register is coupled to an input of said first and second multiplexers.

30. An apparatus for generating address pointers at an output for coupling to an address port of a memory for controlling data operations of said memory comprising:

a clock means for periodically generating a load signal;

a first register means having an input and having a load input coupled to said clock means for storing the address at said input upon each occurrence of said load signal and having an output, said register means for storing a read pointer for a transmit FIFO;

a second register means having an input and having a load input coupled to said clock means for storing the address at said input upon each occurrence of said load signal and having an output, said register means for storing a write pointer for said transmit FIFO;

a third register means having an input and having a load input coupled to said clock means for storing the address at said input upon each occurrence of said load signal and having an output, said register means for storing a read pointer for a receive FIFO;

a fourth register means having an input and having a load input coupled to said clock means for storing the address at said input upon each occurrence of said load signal and having an output, said register means for storing a write pointer for said receive FIFO;

an output multiplexer having inputs coupled to said outputs of said first, second, third and fourth register means and having an output and having a control input for receiving a signal controlling which of said inputs is coupled to said output;

first through fourth input multiplexers for said first through fourth register means, respectively, each input multiplexer having an output coupled to said input of an associated register means and each input multiplexer having first and second inputs and having a control input for receciving a signal controlling which of said inputs is coupled to said outputs;

an incrementing means having an input coupled to the output of said output multiplexer and having an output coupled to each first input of each said input multiplexer, for incrementing the address pointer at the output of said output multiplexer and for supplying the incremented result to said first inputs of said first through fourth input multiplexers;

an initialization bus coupled to each second input of said input multiplexers for allowing any of said registers to be loaded with an address placed on said initialization bus;

control means having an instruction port and having output signal lines coupled to said control inputs for said input multiplexers to cause any selected one of said input multiplexers to select the selected input multiplexers second input for coupling to said output of said selected input multiplexer when a predetermined instruction arrives at said instruction port; and

arbitration means having a plurality of memory access request inputs and having a plurality of control signal lines coupled to said control inputs of said input multiplexers and to said control input of said output multiplexer for arbitrating simulataneous memory access requests with each said request associated with one of said register means, for selecting the highest priority current memory access request and for activating predetermined control signal lines to cause said output multiplexer to select the output of the register means associated with the current highest priority memory access request selected by said arbitration means for output by said output multiplexer and for causing the input multiplexer coupled to the associated register means to select the input coupled to said incrementing means such that the current address in the selected register means will be incremented and the new value will be loaded on the next clock cycle.

31. An apparatus as defined in claim 30 further comprising means coupled to said initialization bus and to said output of said output multiplexer and having a control output for storing an end address for each of said transmit FIFO and said receive FIFO and for comparing the address of the currently selected FIFO to the appropriate one of the end addresses and for generating a signal indicating whether or not the end address has been equalled.

32. An apparatus as defined in claim 31 further comprising random access memory means coupled to said output multiplexer and said incrementing means and to said initialization bus and to said control means, said random access memory means for storing any address on said initialization bus and to be output at the output of said output multiplexer upon receipt of a predetermined instruction at said instruction port of said control means and for storing on each load signal either an incremented or a not incremented version of the address stored therein at the next previous load signal and for re-outputting the address stored upon each occurrence of said load signal depending upon the instruction received.

33. The apparatus of claim 30 further comprising a data bus and a fifth register means coupled to said output multiplexer and selectively coupled through a fifth input multiplexer to said data bus for storing a second read pointer for said transmit FIFO such that two linked lists may be stored in and transmitted from said transmit FIFO.

34. The apparatus of claim 30 further comprising first and second start address registers coupled to said initialization bus for storing first and second start addresses for said transmit and said receive FIFO'"'"'s, respectively, and having first and second outputs, respectively, coupled to inputs of said first, second, third and fourth registers.

35. The apparatus of claim 30 further comprising a shadow write pointer register means for storing predetermined data at predetermined times and having an output coupled to an input of said fourth multiplexer and having a load input coupled to said clock means and having an input which is coupled to the output of said fourth register means, and further comprising a fifth multiplexer means for selectively coupling said shadow write pointer register means to said fourth register means and having a control input coupled to said control means and having a hold input coupled to said shadow write pointer register means output, and wherein said control means is also for generating signals at predetermined times to cause said fourth and fifth multiplexers to switch states so as to cause said fourth register and said shadow write pointer rigister to swap their contents.

36. A method of operating a RAM buffer controller for generating addresses for a memory, said RAM buffer controller being coupled to an output of a data path controller and including a first register, a second register, an incrementer and an output gate for gating the output of the first register to the address inputs of said memory, comprising the steps of:

storing an address in said first register;

upon receipt of a first signal from said data path controller and after storing said address, as a first storing step storing the contents of said first register in said second register and incrementing the contents of said first register;

upon receipt of a second signal from said data path controller after said first storing step, holding the contents of said second register constant while incrementing the contents of said first register once for every access to said memory;

upon receipt of a third signal from said data path controller after receipt of said second signal, simultaneously causing the contents of said first and second registers to be exchanged;

after said exchanging step, as a first gating step gating the output of said first register to said address inputs and writing data into the location in memory addressed by the contents of said first register;

after said first gating and writing step, as a second storing step causing the contents of said second register to be stored in said first register;

after said second storing step, as a second gating step gating the output of said first register to said address inputs of said memory and writing a predetermined bit at a predetermined bit location within the memory location addressed by the contents of said first register with predetermined data; and

after said second gating step, holding the contents of said first register constant.

37. A method of operating a RAM buffer controller for generating addresses for a memory, said RAM buffer controller being coupled to an output of a data path controller and including a first register, a second register, an incrementer and an output gate for gating the output of the first register to the address inputs of said memory, comprising the steps of:

storing a starting address defining the starting address for storing information pertaining to the status and length of a data block comprising sufficient data to require storage in a plurality of memory locations in said memory in said first register;

upon receipt of a first signal from said data path controller after storing said address, storing the starting address stored in said first register in said second register and incrementing the contents of said first register to create a pointer address in said first register which is the next successive address after said starting address in said memory;

upon receipt of a second signal from said data path controller after storing said starting address in said second register, holding the contents of said second register constant while incrementing the contents of said first register once for every access to said memory and storing data from said data block in said memory at said successive addresses in said memory;

upon receipt of a third signal from said data path controller after storing all said data from said data block in successive addresses in said memory, causing the starting address stored in said second register to be stored in said first register; and

storing status and length information pertaining to said data block at said starting address in said memory pointed to by the contents of said first register.

38. A method of operating a RAM buffer controller for generating addresses for a memory, said RAM buffer controller being coupled to an output of a data path controller and including a first register, a second register, an incrementer and an output gate for gating the output of the first register to the address inputs of said memory, comprising the steps of:

storing an address in said first register;

upon receipt of a first signal from said data path controller after storing said address, storing the contents of said first register in said second register and incrementing the contents of said first register;

upon receit of a second signal from said data path controller after storing said first register contents, holding the contents of said second register constant while incrementing the contents of said first register once for every access to said memory;

upon receipt of a third signal from said data path controller after said holding step, causing the contents of said second register to be stored in said first register;

after storing said second register contents, as a first gating step gating the output of said first register through to said address inputs and writing predetermined data in a location in memory addressed by the contents of said first register;

after said first gating step, incrementing the contents of said first register;

after said incrementing step, as a second gating step gating the output of said first register through to said address inputs and writing a predetermined data bit into another memory location addressed by the contents of said first register; and

after said second gating step, preventing the incrementing of the contents of said first register in preparation for the next memory access.

39. A method of operating a RAM buffer controller controlling the address inputs of a memory, said RAM buffer controller being coupled to an output of a data path controller and having a first register for storing write pointer addresses for use in storing received packets from a network in said memory and having a second register for storing a shadow write pointer and having first and second multiplexers controlling the data which is input respectively to said first register and to said second register and having an incrementer having an input and having an output coupled to an input of said first multiplexer where said first multiplexer also has inputs coupled to the output of said first register and to the output of said second register and where said second multiplexer has inputs coupled to the output of said first register and to the output of said second register and having control logic with a plurality of input signal lines and a plurality of output control lines to control the operation of said first and second multiplexers by means of a control program where each of said first and second multiplexers has a clock input coupled to a clock generating load signals and having an output multiplexer with a plurality of inputs including an input coupled to the output of said first register and with an output coupled to the input of said incrementer comprising the steps of:

generating signals by said control logic according to said control program upon receipt of a first signal from said data path controller to cause said second multiplexer to select its input coupled to the output of said first register and to cause the contents of said first register to be stored in said second register and thereafter generatng signals according to said control program to cause said second multiplexer to select its input coupled to the output of said second register and generating control signals according to said control program to cause said first multiplexer to select its input coupled to said incrementer and thereafter generating signals according to said control program causing said first multiplexer to select its input coupled to the output of said first register;

generating signals by said control logic according to said control program upon receipt of a second signal from said data path controller to cause said output multiplexer to select the input coupled to the output of said first register once during every memory cycle and to cause said first multiplexer to again select its input coupled to said incrementer on every memory access cycle and thereafter to hold the contents of said first register constant by selecting the input coupled to the output of said second register between memory cycles, and generating signals to cause said second multiplexer to select its input coupled to the output of said second register while said first multiplexer is selecting its input coupled to said incrementer;

generating signals by said control logic according to said control program upon receipt of a third signal from said data path controller to cause said second multiplexer to select its input coupled to the output of said first register and to cause the contents of said first register to be stored in said second register and to cause the contents of said second register to thereafter be held constant for a predetermined period and simultaneously with the loading of the contents of said first register into said second register to cause said first multiplexer to select its input coupled to the output of said second register and to cause the contents of said second register to be stored in said first register and thereafter to cause the contents of said first register to be held constant for another predetermined period;

generating signals according to said control program to cause said output multiplexer to select the input coupled to the output of said first register and writing status and length information into the memory location in said memory addressed by the contents of said first register;

generating signals according to said control program cuasing said first multiplexer to select its input coupled to the output of said second register so that the contents of said second register will be loaded into said first register and to cause the contents of said first register to be held constant;

writing a predetermined bit into the memory location addressed by the contents of said first register; and

generating signals according to said control program causing said first multiplexer to select its input coupled to the output of said first register to hold the contents of said first register constant.

40. A method of operating a RAM buffer controller controlling the address input of a memory, said RAM buffer controller being coupled to an output of a data path controller, and having a first register for storing write pointer addresses for use in storing received data in said memory, and having a second register for storing a shadow write pointer, and having first and second multiplexers controlling the data which is input respectively to said first register and to said second register, and having an incrementer having an input and having an output coupled to an input of said first multiplexer and wherein said first multiplexer also has input coupled to the output of said first register and to the output of said second register, and wherein said second multiplexer has inputs coupled to the output of said first register and to the output of said second register, and having control logic with a plurality of input signal lines and a plurality of output control lines to control the operation of said first and second multiplexers by means of a control program where each of said first and second multiplexers has a clock input coupled to a clock, said clock for generating load signals, and having an output multiplexer with a plurality of inputs including an input coupled to the output of said first register and an output coupled to the input of said incrementer, comprising the steps of:

generating signals by said control logic according to said control program upon receipt of a first signal from said data path controller to cause said second multiplexer to select its input coupled to the output of said first register and to cause the contents of said first register to be stored in said second register, and, thereafter, generating signals according to said control program to cause said second multiplexer to select its input coupled to the output of said second register, and generating control signals according to said control program to cause said first multiplexer to select its input coupled to said incrementer, and, thereafter, generating signals according to said control program causing said first multiplexer to select its input coupled to the output of said first register;

generating signals by said control logic according to said control program upon receipt of a second signal from said data path controller to cause said output multiplexer to select the input coupled to the output of said first register once during every memory cycle and to cause said first multiplexer to again select its input coupled to said incrementer on every memory access cycle, and, thereafter, to hold the contents of said first register constant by selecting the input coupled to the output of said first register between memory cycles, and generating signals to cause this second multiplexer to select its input coupled to the output of said second register while said first multiplexer is selecting its input coupled to said incrementer;

generating signals by said control logic according to said control program upon receipt of a third signal from said data path controller to cause said first multiplexer to select its input coupled to the output of said second register and to cause the contents of said second register to be stored in said first register, and, thereafter, to cause the contents of said first register to be held constant for a predetermined period.