Simultaneously deposited thin film CMOS TFTs and their method of fabrication

• US 4,951,113 A
• Filed: 11/07/1988
• Issued: 08/21/1990
• Est. Priority Date: 11/07/1988
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Wu, I-Wei, Huang, Tiao-Yuan, Chiang, Anne
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Nguyen, Viet Q.
• Application Number:
  US07/268,832
• Time in Patent Office: 652 Days
• Field of Search: 357/40, 357/42, 357/23.17
• US Class Current: 257/369
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/78663 Amorphous silicon transistors
• CPC Class Codes: H01L 29/78672 Polycrystalline or microcrystalline silicon transistor

Abstract

A thin film SOI CMOS device wheren the suitably doped deposited layers of an n-channel transistor and a p-channel transistor are simultaneously deposited. The source and drain elements of one transistor and the gate element of the other transistor are formed in a lower, highly doped, semiconductor layer and are separated from the corresponding gate element and source and drain elements formed in an upper, highly doped, semiconductor layer. The layer levels are separated by two intrinsic or lightly doped semiconductor layers sandwiching a dielectric layer, so that the intrinsic or lightly doped semiconductor layer lying contiguous to the source and drain elements serves as an active channel layer and the intrinsic or lightly doped semiconductor layer lying contiguous to the gate element serves to extend the gate layer.

Claims

1. A thin film SOI CMOS device including complementary transistors supported upon an insulating substrate, said transistors characterized by comprising:

first source and drain elements of one transistor and first gate element of a complementary transistor all formed of a first doped semiconductor material, of one conductivity type, and disposed at a first level upon said substrate,

second gate element of said one transistor and second source and drain elements of said complementary transistor all formed of a second doped semiconductor material, of the opposite conductivity type, and disposed at a second level above said substrate, and

a tri-layer stack disposed at an intermediate level between said first and said second levels, including a pair of intrinsic or lightly doped semiconductor layers separated by a dielectric layer, and wherein one of said intrinsic or lightly doped layers is contiguous to said first source and drain elements and said first gate element and serves as the active channel layer for said one transistor and the other of said intrinsic or lightly doped layers is contiguous to said second source and drain elements and said second gate element and serves as the active channel layer for said complementary transistor.

2. The thin film SOI CMOS device as defined in claim 1 wherein in said one transistor and in said complementary transistor each of said first gate element and said second gate element is aligned respectively with said first source and drain elements and said second source and drain elements.

3. The thin film SOI CMOS device as defined in claim 1, for use as a high voltage device, wherein in said one transistor and in said complementary transistor each of said first gate element and said second gate element does not extend completely laterally, respectively, from said first source element to said first drain element and from said second source element to said second drain element.