Isolation of insulated-gate field-effect transistors

• US 4,951,117 A
• Filed: 08/19/1988
• Issued: 08/21/1990
• Est. Priority Date: 08/21/1987
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kasai, Naoki
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Tran, Minh Loan
• Application Number:
  US07/234,358
• Time in Patent Office: 732 Days
• Field of Search: 357/49, 357/23.4, 357/23.1, 357/54, 357/55, 357/23.14, 357/42, 357/46
• US Class Current: 257/334
• CPC Class Codes: H01L 21/76294 using selective deposition of single crystal silicon, i.e. SEG techniques
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Abstract

A semiconductor device and a method of fabricating the same wherein a semiconductor substrate of one conductivity type is formed of three laterally arrayed portions by providing two trenches in the substrate and filling them with first and second epitaxial layers of an opposite conductivity type. A buried layer of the opposite conductivity type is formed within the substrate. First and second insulator films are provided on the side walls of both trenches. The first portion of the substrate has a first region of one conductivity type. A second region of the one conductivity type is buried within the substrate. A third region of the opposite conductivity type is interposed in the direction of substrate depth between the first and second insulator films. The portion of the substrate includes a fourth region isolated from the first to third regions by the first insulator film. The third portion of the substrate includes a fifth region of the one conductivity type electrically connected to the second region. The first, second and fourth region work as one and the other of drain and source regions, and the gate of a vertical MOS transistor, respectively, and the fifth region is used for electrical connection to the buried second region.

Claims

1. A semiconductor device comprising a semiconductor substrate having a first portion, a second portion and a third portion arrayed therein laterally and adjacently in this order, a first thin insulator film projecting from a surface of said substrate down into said substrate and interposed between said first portion and said second portion of said substrate, a second thin insulator film projecting from the surface of said substrate down into said substrate more deeply than said first thin insulator film and interposed between said second portion and said third portion of said substrate, a first region of one conductivity type formed at the upper surface of said second portion of said substrate and extending laterally between said first and second thin insulator films a second region of said one conductivity type buried within said second portion of said substrate under said first region and extending in the depthwise direction more deeply than said first thin insulator film and more shallowly than said second thin insulator film, a third region of the opposite conductivity type formed in said second portion of said substrate and interposed in the depthwise direction between said first region and said second region, said third region laterally extending between said first and second thin insulator films, a fourth region formed in said third portion of said substrate so as to contact with said second thin insulator film and to face said third region via said second thin insulator film, said fourth region being isolated from said first, second and third regions by said second thin insulator film, and a fifth region of said one conductivity type formed in said first portion of said substrate and electrically connected to said second region under said fist thin insulator film, said fifth region being electrically isolated from said first region by said first thin insulator film, said first region working as one of a source and a drain of a vertical MOS transistor of one conductivity type channel, said second region working as the other of the source and the drain of said vertical MOS transistor, said fourth region working as the gate of said vertical MOS transistor, and said fifth region serving for electrical connection to said second region.

2. The semiconductor device as claimed in claim 1, in which said first and third portions of said substrate include a first and a second expitaxial layers, respectively, refilling a first and a second trenches formed therein, respectively.

3. The semiconductor device as claimed in claimed 2, wherein said first thin insulator film includes an insulator film formed on one of sidewalls of said first trench and said second thin insulator film includes an insulator film formed on one of sidewalls of said second trench.

4. The semiconductor device as claimed in claim 3, wherein said first and second epitaxial layers are of said one conductivity type and said fourth region has said opposite conductivity type and is formed in said second epitaxial layer.

5. The semiconductor device as claimed in claim 4, further comprising a sixth region of said opposite conductivity type formed in said second epitaxial layer, a gate insulator formed on a part of said second epitaxial layer between said fourth and sixth regions, and a gate electrode formed on said gate insulator, said fourth region, said sixth region and said gate electrode constituting a lateral MOS transistor of the opposite conductivity channel which is isolated from said vertical MOS transistor by said second thin film insulator.