Semiconductor memory device

• US 4,951,251 A
• Filed: 07/26/1988
• Issued: 08/21/1990
• Est. Priority Date: 06/17/1985
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamaguchi, Yasunori, Miyake, Jun
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/224,375
• Time in Patent Office: 756 Days
• Field of Search: 365/189, 365/222, 365/230, 365/233, 365/149, 365/210, 365/189.02, 365/230.02
• US Class Current: 365/189.02
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence

Abstract

A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.

Claims

1. A semiconductor memory device formed on one chip used for image processing comprising:

a memory portion for storing image data;

an internal circuit coupled to said memory portion to provide said image data to said memory portion, wherein said internal circuit has a plurality of operation modes which are respectively selected in accordance with a function signal so that the image data to be provided to said memory portion in each operation mode is determined by said function signal;

an address input terminal; and

a function setting circuit coupled to receive an input signal from said address input terminal, said function setting circuit including means for forming said function signal in accordance with said input signal;

an output terminal; and

a parallel to serial converter coupled between said memory portion and said output terminal for storing signals read out in parallel from said memory portion and for supplying said signals to said output terminal serially.

2. A semiconductor memory device formed on one chip used for image processing as defined in claim 1, wherein said device comprises a timing control circuit which receives a chip selection signal and a first control signal, wherein said timing control circuit is coupled to said function setting circuit and includes means for forming a first timing signal in accordance with said chip selection signal and said first control signal, said first timing signal being provided to said function setting circuit to control the operation of said function setting circuit with respect to receiving said input signal.

3. A semiconductor memory device formed on one chip used for image processing as defined in claim 2, wherein said function setting circuit has a hold means for maintaining the level of said function signal based on said first timing signal until said first timing signal is generated again.

4. A semiconductor memory device formed on one chip used for image processing as defined in claim 2, further comprising an address buffer having an input terminal which is coupled to said address input terminal, the input signal being fed via said address buffer to said function setting circuit.

5. A semiconductor memory device formed on one chip used for image processing as defined in claim 4, wherein said address buffer comprises an address buffer for receiving a row address signal and a column address signal which are fed to said address input terminal in accordance with a time sharing system and further wherein said chip selection signal comprises a row address strobe signal, and said first control signal is composed of a column address strobe signal and a write enable signal.

6. A semiconductor memory device formed on one chip used for image processing as defined in claim 5, wherein said memory portion comprises a dynamic random access memory including a plurality of dynamic memory cells.

7. A semiconductor memory device formed on one chip used for image processing as defined in claim 6, further comprising a refresh control circuit for forming at least a refresh address signal for designating a dynamic memory cell to be refreshed from said memory portion.

8. A video-RAM device according to claim 1, wherein said parallel to serial converter is comprised of a register.

9. A semiconductor memory device according to claim 8, wherein the register includes four shift registers, each of which receives a work of stored image data in parallel from the memory portion to represent one of red, blue and green color data an luminance data, and further wherein the register includes means to convert said parallel received words into serial signals to said output terminal in a synchronized relationship with a predetermined raster scan timing of a CRT coupled to said output terminal.

10. A video-RAM device formed on one chip comprising:

memory means for storing image data;

a plurality of input terminals;

logical operation means coupled to said memory means, and to said input terminals, for providing said image data to be written into said memory means, wherein said logical operation means has a plurality of operation modes which are respectively selected in accordance with a plurality of function signals, and includes means for performing a logical operation selected by said function signals based on input data applied to said input terminals and output data read out from said memory means to form said image data to be written into said memory means;

a plurality of address input terminals;

function signal generating means coupled to receive input signals from said address input terminals, wherein said function signal generating means includes means for generating said function signals on the basis of input signals applied to said address input terminals;

an output terminal; and

a parallel to serial converter coupled between said memory portion and said output terminal for storing signals read out in parallel from said memory portion and for supplying said signals to said output terminal serially.

11. A video-RAM device formed on one chip as defined in claim 10, further comprising control signal generating means coupled to said function signal generating means, wherein said control signal generating means includes means for forming a control signal in accordance with external control signals, and wherein said control signal controls an operation of said function signal generating means with respect to receiving said input signals applied to said address input terminals.

12. A video-RAM device formed on one chip as defined in claim 11, wherein said memory means comprises a dynamic random access memory.

13. A video-RAM device formed on one chip as defined in claim 12, wherein said external control signals include a row address strobe signal, a column address strobe signal, and a write enable signal.

14. A video-RAM device formed on one chip as defined in claim 13, wherein said logical operation means further comprises a transferring means for directly transferring said input data applied to said input terminals to said memory means in accordance with a transferring signal.

15. A video-RAM device formed on one chip as defined in claim 14, further comprising latching means coupled between said logical operation means and said memory means, for latching said output data read out from said memory means so that said latching means provides said output data read out from said memory means to said logical operation means.

16. A video-RAM device formed on one chip as defined in claim 15, further comprising masking means for inhibiting predetermined input data applied to said input terminals at least in accordance with masking signals.

17. A video-RAM device formed on one chip as defined in claim 16, further comprising address buffer means coupled to said memory means, to said function signal generating means, and to said address input terminals, wherein said input signals are fed to said function signal generating means via said address buffer means.

18. A video-RAM device formed on one chip as defined in claim 17, further comprising a refresh control means for forming at least a refresh signal for designating a dynamic memory cell to be refreshed from said memory means, wherein said refresh control means forms said refresh signal when said control signal generating means forms said control signal.

19. A semiconductor memory device according to claim 10, wherein said parallel to serial converter is comprised of a register.

20. A video RAM device according to claim 19, wherein the register includes four shift registers, each of which receives a word of stored image data in parallel from the memory means to represent one of red, blue and green color data and luminance data, and further wherein the register includes means to convert said parallel received words into serial signals to said output terminal in a synchronized relationship with a predetermined raster scan timing of a CRT coupled to said output terminal.

21. A semiconductor memory device used for image processing comprising:

a memory portion for storing image data, wherein said memory portion includes means to allow a plurality of image data stored therein to be rewritten;

an operation circuit coupled to receive input data applied to input terminals and output data read out from said memory portion, wherein said operation circuit includes means for performing a logical operation based on said input and output data to form operation image data to be written into said memory portion;

a function setting circuit;

a bypass circuit the operation of which is controlled by a control signal fed from said function setting circuit to feed said input data directly to said memory portion in accordance with a predetermined level of said control signal;

an output terminal; and

a parallel to serial converter coupled between said memory portion and said output terminal for storing signals read out in parallel from said memory portion and for supplying said signals to said output terminal serially.

22. A semiconductor memory device used for image processing as defined in claim 21, wherein said operation circuit has a plurality of operation modes and said function setting circuit outputs operation control signals for selecting predetermined ones of said operation modes in accordance with said operation control signals.

23. A semiconductor memory device used for image processing as defined in claim 22, further comprising a timing control circuit the operation of which is controlled by a plurality of external control signals, wherein, when said plurality of external control signals are set to a predetermined state, a timing control signal is formed by said timing control circuit for setting said function setting circuit to perform a predetermined input operation, said function setting circuit having a hold means for maintaining an operation control signal and said control signal for said bypass circuit after said input operation.

24. A semiconductor memory device used for image processing as defined in claim 23, further comprising an address input terminal and a coupling means including an address buffer for coupling said address input terminal and the input terminal of said function setting circuit.

25. A semiconductor memory device according to claim 21, wherein said parallel to serial converter is comprised of a register.

26. A semiconductor memory device according to claim 25, wherein the register includes four shift registers, each of which receives a word of stored image data in parallel from the memory portion to represent one of red, blue and green color data and luminance data, and further wherein the register includes means to convert said parallel received words into serial signals to said output terminal in a synchronized relationship with a predetermined raster scan timing of a CRT coupled to said output terminal.

27. A video-RAM device formed on one chip comprising:

a memory means for storing data;

a plurality of input terminals;

logical operation means coupled to said memory means, and to said input terminals, for providing data to be written into said memory means, wherein said logical operation means has a plurality of operation modes which are respectively selected in accordance with a plurality of function signals, and includes means for performing a logical operation selected by said function signals based on input data applied to said input terminals and output data read out from said memory means to form said data to be written into said memory means;

a plurality of address input terminals; and

function signal generating means coupled to receive input signals from said address input terminals, wherein said function signal generating means includes means for generating said function signals on the basis of input signals applied to said address input terminals, further comprising control signal generating means coupled to said function signal generating means wherein said control signal generating means includes means for forming a control signal in accordance with external control signals, and wherein said control signal controls an operation of said function signal generating means with respect to receiving said input signals applied to said address input terminals.

28. A video-RAM device formed on one chip as defined in claim 27, wherein said memory means comprises a dynamic random access memory.

29. A video-RAM device formed on one chip as defined in claim 28, wherein said external control signals include a row address strobe signal, a column address strobe signal, and a write enable signal.

30. A video-RAM device formed on one chip as defined in claim 29, wherein said logical operation means further comprises a transferring means for directly transferring said input data applied to said input terminals to said memory means in accordance with a transferring signal.

31. A video-RAM device formed on one chip as defined in claim 30, further comprising latching means coupled between said logical operation means and said memory means, for latching said output data read out from said memory means so that said latching means provides said output data read out from said memory means to said logical operation means.

32. A video-RAM device formed on one chip as defined in claim 31, further comprising masking means for inhibiting predetermined input data applied to said input terminals at least in accordance with masking signals.

33. A video-RAM device formed on one chip as defined in claim 32, further comprising address buffer means coupled to said memory means, to said function signal generating means, and to said address input terminals, wherein said input signals are fed to said function signal generating means via said address buffer means.

34. A video-RAM device formed on one chip as defined in claim 33, further comprising a refresh control means for forming at least a refresh signal for designating a dynamic memory cell to be refreshed from said memory means, wherein said refresh control means forms said refresh signal when said control signal generating means forms said control signal.

35. In an address multiplexed dynamic RAM, a circuit arrangement comprising:

a memory portion for storing data;

a logic circuit coupled to said memory portion and having a plurality of operation modes which are respectively selected in accordance with a mode selecting signal;

control mans coupled to said logic circuit for controlling said logic circuit;

a first external terminal coupled to said control means for receiving a row address strobe signal;

a second external terminal coupled to said control means for receiving a column address strobe signal;

a third external terminal coupled to said control means for receiving a write enable signal; and

a fourth external terminal coupled to said control means for receiving said mode selecting signal;

wherein a predetermined one of said operation modes is selected by said control means in response to said column address strobe signal, coupled to said control means by said second external terminal being at a logic "low " level and said write enable signal, coupled to said control means by said third external terminal, being at a logic "low " level when said row address strobe signal, coupled to said control means by said first external terminal, is at a transitional logic level corresponding to a falling edge and when said mode selecting signal, coupled to said control means by said fourth external terminal, is at a predetermined logic level.

36. An address multiplexed dynamic RAM according to claim 35, wherein said fourth external terminal is an address input terminal.

37. An address multiplexed dynamic RAM according to claim 36, wherein the data to be provided to said memory portion in each operation mode is determined by said mode selecting signal.

38. An address multiplexed dynamic RAM according to claim 37, wherein said address multiplexed dynamic RAM is formed on one chip used for image processing.

39. In an address multiplexed dynamic RAM, a circuit arrangement comprising:

a first external terminal for receiving a row address strobe signal;

a second external terminal for receiving a column address strobe signal;

a third external terminal for receiving a write enable signal;

a fourth external terminal for receiving a mode selecting signal;

a fifth external terminal for receiving input data;

a memory portion for storing data;

a logic portion coupled to said memory portion and having mans for performing a logic operation selected by said mode selecting signal based on said input data and output data read out from said memory portion to form said data to be written into said memory portion; and

control means coupled to said first, second, third and fourth external terminal and to said logic portion for controlling said logic portion,

wherein said logic operation is selected in response to said column address strobe signal, coupled to said control means by said second external terminal, being at a logic "low" level and said mode selecting signal, coupled to said control means by said fourth external terminal, being at a predetermined logic level when said row address strobe signal, coupled to said control mans by said first external terminal, is at a transitional logic level corresponding to a falling edge.

40. An address multiplexed dynamic RAM according to claim 39, wherein said fourth external is an address input terminal.

41. An address multiplexed dynamic RAM according to claim 40, wherein said address multiplexed dynamic RAM is formed on one chip used for image processing.

42. A method of selecting one of a plurality of operation modes in an address multiplexed dynamic RAM having a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal, a third external terminal for receiving a write enable signal, a fourth external terminal for receiving a mode selecting signal, and a logic portion having said plurality of operation modes which are respectively selected in accordance with said modes selecting signal, said method of selecting one of said plurality of operation modes comprising the steps of:

(a) making said column address strobe signal a logic "low" level;

(b) making said write enable signal a logic "low" level; and

(c) making said row address strobe signal a logic "low" level after said steps (a) and (b).