High speed digital programmable frequency divider

• US 4,951,303 A
• Filed: 10/31/1988
• Issued: 08/21/1990
• Est. Priority Date: 10/31/1988
• Status: Expired due to Term

• Current Assignee: Hughes Electronics Corporation (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company Los Angeles California
• Inventors: Larson, Lawrence E.
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US07/264,935
• Time in Patent Office: 659 Days
• Field of Search: 377/47, 377/48, 377/72, 377/73, 377/74, 377/78, 377/79, 377/104, 377/105, 377/110
• US Class Current: 377/110
• CPC Class Codes: H03K 23/44 using field-effect transistors H03K23/46 and H03K23/425 take precedence
• CPC Class Codes: H03K 23/544 with a base which is an odd number
• CPC Class Codes: H03K 23/667 by switching the base during a counting cycle

Abstract

A high speed digital programmable frequency divider (100) capable of frequency division by even and odd integers is disclosed herein. The frequency divider (100) of the present invention includes a waveform generator (200) for providing a periodic input waveform of a first period and the inverse thereof. The present invention further includes a clocked ring oscillator circuit (400) for providing first and second closed signal paths, in response to the input waveform, disposed to invert signals passing therethrough. The first and second signal paths have a common output node (499) and first and second propagation delays substantially equal to first and second integral multiples of the first period, respectively. In addition, the frequency divider (100) includes a programmable switch network (500) for opening the first and second signal paths to provide a periodic output waveform at the output node (499).

Claims

1. A high speed frequency divider comprising:

means for providing a periodic input waveform having a first period on a first line and the complement thereof on a second line and

a clocked ring oscillator including

first, second, third and fourth transmission gates connected in a series relation, each having an input terminal, with the input terminals of said first and third gates being connected to said second line and the input terminals of said second and fourth gates being connected to said first line,

first, second and third inverters connected between said first and second gates, said second and third gates, and said third and fourth gates respectively, said first inverter connected to a first terminal of said first gate and said third inverter being connected to a first terminal of said fourth gate,

a first switch having a first terminal connected to the junction between said second gate and said second inverter,

a second switch having a first terminal connected to a second terminal of said fourth gate, a second terminal of said first switch connected to a second terminal of said second switch,

a buffer connected between the second terminals of said first and second switches and a second terminal of said first gate, said output of said buffer providing the output of said oscillator and

means for applying complementary inputs to said first and second switches.

2. The invention of claim 1 including third switch means for selectively connecting the output of said buffer to the inputs of said first switch.

3. A method for providing high speed frequency division including the steps of:

(a) driving a clocked ring oscillator with a periodic waveform and the complement thereof, said oscillator including;

first, second, third and fourth transmission gates connected in a series relation, each having an input terminal, with the input terminals of said first and third gates being connected to a source of said periodic waveform and the input terminals of said second and fourth gates being connected to a source of said complement of said periodic waveform,

first, second and third inverters connected between said first and second gates, said second and third gates, and said third and fourth gates respectively, said first inverter connected to a first terminal of said first gate and said third inverter being connected to a first terminal of said fourth gate,

a first switch having a first terminal connected to the junction between said second gate and said second inverter,

a second switch having a first terminal connected to a second terminal of said fourth gate, a second terminal of said first switch connected to a second terminal of said second switch,

a buffer connected between the second terminals of said first and second switches and a second terminal of said first gate, said output of said buffer providing the output of said oscillator and

means for applying complementary inputs to said first and second switches and

(b) feeding the output of said oscillator to the input thereof.