Vertical field-effect transistor having a high breakdown voltage and a small on-resistance

• US 4,952,991 A
• Filed: 08/23/1989
• Issued: 08/28/1990
• Est. Priority Date: 08/25/1988
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Kayama, Chizuru
• Primary Examiner(s): Wojciechowicz, Edward J.
• Application Number:
  US07/397,232
• Time in Patent Office: 370 Days
• Field of Search: 357/23.4, 357/86, 357/89
• US Class Current: 257/335
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A vertical MOSFET includes a base region formed on the surface of a drain region, a source region provided in the base region, a first semiconductor region provided on the surface of the drain region between portions of the base region, the first semiconductor region having the same conductivity type as the drain region and an impurity concentration higher than that of the drain region, a second semiconductor region of the opposite conductivity type provided in the first semiconductor region, a gate electrode provided on the base region surrounded by the source region and the first semiconductor region, and an insulating film provided on the second semiconductor region.

Claims

1. A field effect transistor comprising:

a first semiconductor region formed on a main surface of a semiconductor substrate of one conductivity type except for a predetermined portion of said semiconductor substrate, said first semiconductor region being of the other conductivity type;

a second semiconductor region formed on said main surface of said semiconductor substrate uncovered by said first semiconductor region, said second semiconductor region having said one conductivity type with an impurity concentration higher than said semiconductor substrate;

a third semiconductor region of the other conductivity type formed in said second semiconductor region;

a fourth semiconductor region formed on a surface of said first semiconductor region, said fourth semiconductor region being separated from said second semiconductor region and said fourth semiconductor region being of said one conductivity type;

a gate electrode formed on said first semiconductor region between said second semiconductor region and said fourth semiconductor region;

an insulating film provided on said second semiconductor region and on said third semiconductor region;

a first electrode electrically connected to the fourth semiconductor region; and

a second electrode electrically connected to the other main surface of said semiconductor substrate.

2. A field effect transistor as claimed in claim 1, wherein said third semiconductor region is shallower than said second semiconductor region.

3. A vertical field effect transistor comprising:

a drain region of one conductivity type;

a base region of the other conductivity type provided on one main surface of said drain region;

a source region of said one conductivity type provided in said base region;

a first semiconductor region of said one conductivity type provided on said one main surface of said drain region between portions of said base region, said first semiconductor region having an impurity concentration higher than that of said drain region;

a second semiconductor region of the other conductivity type provided in said first semiconductor region;

a gate electrode provided on said base region between said source region and said first semiconductor region;

an insulating film provided on said second semiconductor region;

a source electrode electrically connected to said source region; and

a drain electrode electrically connected to said drain region.

4. A vertical field effect transistor as claimed in claim 3, wherein said second semiconductor region is shallower than said first semiconductor region.