Data driven processor

• US 4,953,083 A
• Filed: 06/28/1989
• Issued: 08/28/1990
• Est. Priority Date: 04/23/1987
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tamura, Toshiyuki, Shima, Kenji, Takata, Hidehiro, Komori, Shinji, Yamasaki, Tetsuo
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US07/373,616
• Time in Patent Office: 426 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/7
• CPC Class Codes: G06F 9/4494 data driven

Abstract

An improved data driven processor that utilizes queue buffers in the data path to maintain optimal dataflow.

Claims

1. An improved data driven processor comprising:

a program storage unit (PSU) that receives a series of processed packets, with each received processed packet including a processing field designating a plurality of N destination nodes in a program and the processing to be executed at each of the designated nodes and including a single data word, said program storage unit for copying the single data word of each received processed packet to N PSU packets and for outputting said N copied PSU packets, with each PSU packet designating a different one of said N destination nodes designated by the processing field of each received processed packet and including processing information for each designated destination node, where the magnitude of N indicates the degree of parallelism of the program and is a measure of the output rate of the program storage unit;

a pair of detecting unit, coupled to said PSU to receive said PSU packets output by said PSU and having stored therein a plurality of stored PSU packets, the pair detecting unit for identifying a given received PSU packet and a given one of said stored PSU packets that each designate the same given one of the N destination nodes in the program and for generating a paired data packet including a processing field designating said given destination node and a data field including a first paired word being the single data word included in said given PSU packet and a second paired word being the single data word included in said given stored PSU packet;

a first datapath for receiving paired packets at a rate not to exceed Fmax, where processing at said program storage unit is slowed or stopped if paired packets are received at said first datapath at a rate exceeding Fmax;

an input buffer, having an input coupled to said pair detecting unit to receive paired packets from said pair detecting unit and an output coupled to said first datapath, for transferring said received paired packets to said first datapath at a stable first buffer output rate with said input buffer having a minimum paired packet capacity required to prevent paired packets from being received at said first datapath at a rate exceeding Fmax;

a processing unit, coupled to said input buffer by said first datapath to receive said paired data packets, for executing the processing operations specified in the processing field of each received paired packet on the first and second words of each received paired packet to generate processed packets, each processed packet including a single processed data word resulting from said processing and including a processing field designating a second plurality of destination nodes in a program, with said processing unit capable of receiving and processing paired data packets and of outputting processed packets at a rate equal to Fmax and with the storage area required to store a paired packet being about double the storage area required to store a processed packet; and

an output buffer, having an input coupled to said processing unit to receive said processed packets at the output rate of said processing unit and having an output coupled to said PSU to transfer received processed packets to said PSU, said output buffer for storing processed packets when processing is slowed or stopped at said program storage unit so that said processing unit may continue outputting processed packets at Fmax, with all of a combined buffer packet storage capacity required to prevent a data flow bottleneck allocated to said output buffer except for said minimum packet capacity required to prevent paired packets from being received at said first datapath at a rate exceeding Fmax so that the storage area required to implement said combined buffer packet storage capacity is reduced.

2. The invention of claim 1 with said input buffer having capacity to store five paired packets and with said output buffer having capacity to store one hundred processed packets.

3. The invention of claim 2 wherein said input buffer is a delay line for providing data at a steady rate to said processing unit.