Variable delay circuit for delaying input data
First Claim
1. A variable delay circuit for delaying input data comprising:
- means for receiving input data externally;
memory device means comprising a memory-cell array for storing the input data;
control means for generating a control signal in response to a clock signal;
data input means connected to said means for receiving input data and responsive to the control signal generated from said control means for writing the input data to the memory cell specified by a signal for specifying a memory cell in said memory device means;
data output means responsive to the control signal generated from said control means for reading the input data written in the memory cell specified by a signal for specifying a memory cell in said memory device means and outputting the same, said control means being adapted to control an operation timing so that the writing operation of the input data may be performed by said data input means after the reading operation is performed to the specified memory cell in said data output means;
means for generating delay data; and
memory cell specifying means connected to said memory device means and said means for generating delay data and responsive to a clock signal, for applying to said memory device means the signal specifying a memory cell as a function of the delay data, wherein said memory cell specifying means comprises address counter means responsive to the clock signal for counting address and outputting an address signal;
coincidence detecting means connected to said means for generating delay data and to said address counter means and responsive to the clock signal for comparing the delay data with the address signal and, when the coincidence is detected, applying to said address counter means a reset signal resetting said address counter means to the predetermined value; and
decoder means connected to said address counter means and responsive to the clock signal for decoding the address signal and applying to said memory device means the signal specifying a memory cell.
1 Assignment
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Accused Products
Abstract
An address counter (2) counts the clock pulses sequentially to provide a count value as an address signal to a coincidence detecting circuit (3) and decoder (4). The coincidence detecting circuit (3) compares delay data applied from a delay data generating circuit (8) with the address signal and applies a reset signal to the address counter (2) when they coincide with each other. The address counter (2) repeats sequentially the above-mentioned operation in response to the reset signal after the count of address is reset to a predetermined value. The decoder (4) specifies a memory cell comprised in a memory device for performing a reading and writing operation in response to the address signal. The data output circuit (6) and the data input circuit (5) perform the reading and writing operation sequentially to the specified memory cell in response to the control signal outputted from the control circuit (7). As a result, the input data previously written is read and outputted with a delay. Therefore, a delayed input data can be obtained as an output data.
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Citations
9 Claims
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1. A variable delay circuit for delaying input data comprising:
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means for receiving input data externally; memory device means comprising a memory-cell array for storing the input data; control means for generating a control signal in response to a clock signal; data input means connected to said means for receiving input data and responsive to the control signal generated from said control means for writing the input data to the memory cell specified by a signal for specifying a memory cell in said memory device means; data output means responsive to the control signal generated from said control means for reading the input data written in the memory cell specified by a signal for specifying a memory cell in said memory device means and outputting the same, said control means being adapted to control an operation timing so that the writing operation of the input data may be performed by said data input means after the reading operation is performed to the specified memory cell in said data output means; means for generating delay data; and memory cell specifying means connected to said memory device means and said means for generating delay data and responsive to a clock signal, for applying to said memory device means the signal specifying a memory cell as a function of the delay data, wherein said memory cell specifying means comprises address counter means responsive to the clock signal for counting address and outputting an address signal;
coincidence detecting means connected to said means for generating delay data and to said address counter means and responsive to the clock signal for comparing the delay data with the address signal and, when the coincidence is detected, applying to said address counter means a reset signal resetting said address counter means to the predetermined value; anddecoder means connected to said address counter means and responsive to the clock signal for decoding the address signal and applying to said memory device means the signal specifying a memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A variable delay circuit for delaying the transmission of input data blocks received sequentially at uniform time intervals in accordance with a clock signal comprising:
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memory device means comprising an array of memory cells in a matrix of rows and columns for storing the input data; means for successively writing each received data block to different specified address locations in said memory device in response to said clock signal; output means for reading out data blocks stored in said memory device; delay setting means for establishing a time delay, equal to a selectable number of said intervals, to transpire for the readout of input data blocks by said output means; means for setting the number of said different specified address locations for each received data block equal to the number of delay intervals set by said delay setting means; and means responsive to said clock signal for writing newly received data at the address locations of the last previously read data block address locations in said memory device.
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9. A method for delaying the transmission of data blocks received sequentially at uniform time intervals comprising the steps of:
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setting a time delay equal to a desired number of said time intervals during which the transmission of said data is to be delayed; specifying address block locations, in a matrix of memory cells for storage of said data, equal in number to the number of time intervals of said delay; successively writing each received data block to different specified address locations in said matrix at each interval; and reading out data stored at the address locations in said matrix immediately prior to rewriting newly received data therein.
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Specification