Memory circuit with extended valid data output time

• US 4,953,130 A
• Filed: 06/27/1988
• Issued: 08/28/1990
• Est. Priority Date: 06/27/1988
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Houston, Theodore W.
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Garcia, Alfonso
• Application Number:
  US07/211,619
• Time in Patent Office: 792 Days
• Field of Search: 365/194, 365/203, 365/189.05, 365/233.5, 307/479, 307/530, 307/272.1, 307/279, 307/590, 307/601, 307/603, 307/445
• US Class Current: 365/203
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches

Abstract

A memory device (10) having an asymmetrical delay circuit (34) in a data output path of the memory device (10) is disclosed. The memory device (10) employs a precharge circuit (28) to impress a precharge state in a read memory access cycle. The asymmetrical delay circuit (34) imposes a relatively slow propagation delay on data signals which transition toward this precharge state, but imposes a relatively fast propagation delay on data signals which transition away from this precharge state. Specific embodiments of an output portion (32) of the memory device (10) are presented to accommodate a high impedance state in an output buffer (38) during signal transitions and to accommodate various polarity precharge states.

Claims

1. A memory device for recalling data stored therein, said memory device comprising:

a memory cell array having a plurality of memory cells, each of said cells being for storing data therein, and each of said cells being coupled to a bit line of said memory cell array;

a sensing circuit, coupled to said bit line of said memory cell array, for sensing data presented thereon;

an asymmetrical delay circuit having an input coupled to said sensing circuit and having an output, said asymmetrical delay circuit, being operable for causing data at said asymmetrical delay circuit output to transistion from a first logical state to a second logical state faster than dat at said asymmetrical delay circuit output transitions from said second logical state to said first logical state, said asymmetrical delay circuit being additionally operable to switch said electrical circuit into it precharge state at a rate faster than it switches said electrical circuit out of said state;

an output buffer coupled to said asymmetrical delay circuit output for presenting data recalled from said memory device; and

a precharge circuit coupled to said delay circuit and to at least one of said bit lines of said memory cell array and said sensing circuit, said precharge circuit causing a predetermined logic level at said asymmetrical delay circuit input prior to recalling data stored in one of said memory cells.

2. A memory device as claimed in claim 1 wherein said asymmetrical delay circuit is configured so that said predetermined logic level causes said output of said asymmetrical delay circuit to exhibit said first logical state.

3. A memory device as claimed in claim 1 wherein said predetermined logic level is a logical 1 value, and said asymmetrical delay circuit comprises:

a delay circuit having an input coupled to said sensing circuit and having an output; and

a logical AND element having a first input coupled to said delay circuit input, a second input coupled to said delay circuit output, and an output which serves as said asymmetrical delay circuit output.

4. A memory device as claimed in claim 3 wherein said output buffer comprises:

a first active device having a control node coupled to said logical AND element output and having an output node;

a second active device having a control node coupled to said delay circuit input and having an output node coupled to said first active device output node so that said first actiVe device activates and said second active device deactivates when said predetermined logic level is presented at said asymmetrical delay circuit input.

5. A memory device as claimed in claim 4 wherein said first active device is a PMOS transistor and said second active device is an NMOS transistor.

6. A memory device as claimed :

n claim 1 wherein said predetermined logic level is a logical 0 value, and said asymmetrical delay circuit comprises;

a delay circuit having an input coupled to said sensing circuit and having an output; and

a logical OR element having a first input coupled to said delay circuit input, a second input coupled to said delay circuit output, and an output which serves as said asymmetrical delay circuit output.

7. A memory device as claimed in claim 6 wherein said output buffer comprises:

a first active device having a control node coupled to said delay circuit input and having an output node;

a second active device having a control node coupled to said logical OR element output and having an output node coupled to said first active device output node so that said second active device activates and said first active device deactivates when said predetermined logic level is presented at said asymmetrical delay circuit input.

8. A memory device as claimed in claim 7 wherein said first active device is a PMOS transistor and said second active device is an NMOS transistor.

9. A memory device as claimed in claim 1 wherein said output buffer comprises:

a first active device having a control node and an output node;

a second active device having a control node and having an output node coupled to said first active device output node so that said output nodes of said first and second devices together present data recalled from said memory device; and

means, coupled between at least one of said first and second active device control nodes and said asymmetrical delay circuit output, for causing one of said first and second active devices to deactivate prior to activation of the other of said first and second active devices.

10. A memory device as claimed in claim 9 wherein:

said asymmetrical delay circuit is configured so that said predetermined logic level causes said first active device to activate and said second active device to deactivate; and

said means for causing is configured so that said second active device deactivates prior to activation of said first active device.

11. A memory device as claimed in claim 10 wherein said means for causing is configured so that said first active device deactivates at approximately the same time as said second active device activates.

12. A memory device as claimed in claim 1 wherein:

said memory device permits recall of data stored therein without said precharge circuit causing said predetermined logic level at said asymmetrical delaY circuit input prior to recalling data stored in one of said memory cells; and

said asymmetrical delaY circuit comprises means for causing data at said asymmetrical delay circuit output to transition from said first logical state to said second logical state in approximatelY the same duration as data transitions from said second logical state to said first logical state when data is recalled from said memory device without said precharge circuit causing said predetermined logic level at said asymmetrical delay circuit input prior to recalling data stored in said memory device.