MOS device for long-term learning

• US 4,953,928 A
• Filed: 06/09/1989
• Issued: 09/04/1990
• Est. Priority Date: 06/09/1989
• Status: Expired due to Term

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Mead, Carver A., Anderson, Janeen D. W.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US07/363,678
• Time in Patent Office: 452 Days
• Field of Search: 357/23.5, 357/43, 365/185
• US Class Current: 257/321
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/8616 Charge trapping diodes

Abstract

A semiconductor structure for long-term learning includes a p-type silicon substrate or well having first and second spaced apart n-type regions formed therein. A polysilicon floating gate is separated from the surface of the silicon substrate by a layer of gate oxide. One edge of the polysilicon floating gate is aligned with the edge of the first n-type region such that the polysilicon floating gate does not appreciably overly the n-type region. The second n-type region lies beyond the edge of the polysilicon floating gate. The first n-type region, the silicon substrate, and the second n-type region form the collector, base, and emitter, respectively, of a lateral bipolar transistor.

An alternate embodiment of a semiconductor long-term learning structure includes an n-type silicon substrate having a p-well region formed therein. An n-type region is formed within the well region. A polysilicon floating gate is separated from the surface of the silicon substrate by a gate oxide and is positioned above the well region. One edge of the polysilicon floating gate is aligned with the edge of the n-type region within the well region such that the polysilicon floating gate does not appreciably overly the n-type region. The substrate, the well, and the n-type region, respectively, form the emitter, base, and collector of a bipolar transistor.

Claims

1. A semiconductor structure for long term learning including:

a p-type region in a semiconductor substrate,

a first n-type region disposed in said p-type region,

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said first n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said first n-type region,

means for applying a first positive potential to said first n-type region with respect to said p-type region to reverse bias said first n-type region, said first positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown in the junction between said first n-type region and said p-type region,

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region,

a second n-type region in contact with said p-type region,

means for applying a negative potential to said second n-type region with respect to said p-type region to forward bias said second n-type region, and to thereby inject minority electrons into said p-type region,

an insulating layer over said floating gate,

a conductive region disposed over said insulating layer and capacitively coupled to said floating gate,

means for selectively applying a third positive potential to said conductive region with respect to said floating gate,

whereby said first and second positive potentials act to accelerate said minority electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said minority electrons onto said floating gate and whereby said third positive potential causes electrons to tunnel from said floating gate to said conductive region.

5. The semiconductor structure of claim 1 wherein said means for capacitively coupling a second positive potential to said floating gate comprises a conductor coupled to said floating gate by a first capacitance.

6. The semiconductor structure of claim 5 wherein said conductive region is capacitively coupled to said floating gate by a second capacitance having a magnitude less than the magnitude of said first capacitance.

2. A semiconductor structure for long term learning including:

a p-type region in a semiconductor substrate,

an n-type region disposed in said p-type region,

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region,

means for applying a first positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown in the junction between said n-type region and said p-type region,

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region,

means for injecting minority electrons into said p-type region,

an insulating layer over said floating gate,

a conductive region disposed over said insulating layer and capacitively coupled to said floating gate,

means for selectively applying a third positive potential to said conductive region with respect to said floating gate,

whereby said first and second positive potentials act to accelerate said minority electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said minority electrons onto said floating gate and whereby said third positive potential causes electrons to tunnel from said floating gate to said conductive region.

7. The semiconductor structure of claim 2 wherein said means for capacitively coupling a second positive potential to said floating gate comprises a conductor coupled to said floating gate by a first capacitance.

8. The semiconductor structure of claim 7 wherein said conductive region is capacitively coupled to said floating gate by a second capacitance having a magnitude less than the magnitude of said first capacitance.

3. A semiconductor structure for long term learning including:

an n-type semiconductor substrate,

a p-type well region in said semiconductor substrate,

an n-type region disposed in said p-type well region,

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region,

means for capacitively coupling a first positive potential to said floating gate, said first positive potential having a magnitude of greater than about 3.2 volts relative to said p-well,

means for applying a second positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said second positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown in the junction between said n-type region and said p-type region,

means for applying a third positive potential to said p-type well region with respect to said semiconductor substrate to forward bias said p-type well region, and to thereby inject minority electrons into said p-type region,

an insulating layer over said floating gate,

a conductive region disposed over said insulating layer and capacitively coupled to said floating gate,

means for selectively applying a third positive potential to said conductive region with respect to said floating gate,

whereby said first and second positive potentials act to accelerate said minority electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said minority electrons onto said floating gate and whereby said third positive potential causes electrons to tunnel from said floating gate to said conductive region.

9. The semiconductor structure of claim 3 wherein said means for capacitively coupling a second positive potential to said floating gate comprises a conductor coupled to said floating gate by a first capacitance.

10. The semiconductor structure of claim 9 wherein said conductive region is capacitively coupled to said floating gate by a second capacitance having a magnitude less than the magnitude of said first capacitance.

4. A semiconductor structure for long term learning including:

an p-type region in a semiconductor substrate,

a first n-type region disposed in said p-type region, said floating gate at least partially overlapping one edge of said first n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said fist n-type region,

means for applying a first positive potential to said first n-type region with respect to said p-type region to reverse bias said first n-type region, said first positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown in the junction between said first n-type region and said p-type region,

means for capacitively coupling a second positive potential to said floating gate, said second positive potential having a magnitude of greater than about 3.2 volts relative to said p-type region,

a second n-type region disposed in said p-type region, laterally spaced from said first n-type region,

means for applying a negative potential to said second n-type region with respect to said p-type region to forward bias said second n-type region, and to thereby inject minority electrons into said p-type region,

an insulating layer over said floating gate,

a conductive region disposed over said insulating layer and capacitively coupled to said floating gate,

means for selectively applying a third positive potential to said conductive region with respect to said floating gate,

whereby said first and second positive potentials act to accelerate said minority electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said minority electrons onto said floating gate and whereby said third positive potential causes electrons to tunnel from said floating gate to said conductive region.

11. The semiconductor structure of claim 4 wherein said means for capacitively coupling a second positive potential to said floating gate comprises a conductor coupled to said floating gate by a first capacitance.

12. The semiconductor structure of claim 11 wherein said conductive region is capacitively coupled to said floating gate by a second capacitance having a magnitude less than the magnitude of said first capacitance.