Method of forming a three dimensional integrated circuit structure

• US 4,954,458 A
• Filed: 04/04/1988
• Issued: 09/04/1990
• Est. Priority Date: 06/03/1982
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Reid, Lee R.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Dang, Trung
• Application Number:
  US07/176,976
• Time in Patent Office: 883 Days
• Field of Search: 357/32, 357/55, 357/56, 357/68, 357/75, 437/51, 437/52, 437/915, 148/DIG. 164
• US Class Current: 438/109
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/10158 at the passive surface
• CPC Class Codes: Y10S 148/164 Three dimensional processing
• CPC Class Codes: Y10S 438/975 Substrate or mask aligning feature

Abstract

A semiconductor circuit apparatus including several semiconductor substrates interconnected by having elevated portions of one substrate contacting the surface of the second substrate where both substrates include at least one electrical circuit. Also included is a method for forming this three dimensional integrated circuit structure by forming the elevated portions of the semiconductor substrate by applying an orientation-dependent etch and then applying an electrically conductive coating to this elevated portion. Electrically conductive bonding pads are formed on the second semiconductor substrate. These pads are selectively positioned relative to the elevated portions formed on the first semiconductor substrate. Contacts between the first and second substrate are formed by forming bonds between the elevated portions on the one substrate and the electrically conductive pads on the second substrate.

Claims

1. A method for forming a semiconductor circuit apparatus comprising:

(a) forming at least one elevated portion upon a first semiconductor substrate by applying an orientation dependent etch;

(b) applying an electrically conductive coating to said elevated portion;

(c) forming electrically conductive bonding pads on a second semiconductor substrate that are selectively positioned relative to the elevated portions formed on the first semiconductor substrate; and

(d) forming contacts between said first substrate and said second substrate by forming an electrically conductive bond between said elevated portions on said first substrate with said electrically conductive pads on said second substrate.

2. A method for forming a semiconductor circuit apparatus comprising:

(a) forming at least one hole in a first semiconductor substrate by applying an orientation dependent etch;

(b) applying an electrically conductive coating from one side of said first semiconductor substrate through said hole to the opposite side of said first semiconductor substrate;

(c) forming at least one elevated portion upon said first semiconductor substrate by applying an orientation dependent etch;

(d) applying an electrically conductive coating to said elevated portion;

(e) forming electrically conductive bonding pads on a second semiconductor substrate that are selectively positioned relative to the elevated portions formed on the first semiconductor substrate; and

(f) forming contacts between said first substrate and said second substrate by forming an electrically conductive bond between said elevated portions on said first substrate with said electrically conductive pads on said second substrate.

3. A method for forming a composite semiconductor circuit structure comprising:

forming a plurality of elevated portions upon one major surface of a first semiconductor substrate having first and second major surfaces by applying an orientation dependent etch to said one major surface of said first semiconductor substrate;

applying a coating of electrically conductive material to the surface area of each of said elevated portions formed on said first semiconductor substrate;

forming a plurality of electrically conductive bonding pads on the other major surface of a second semiconductor substrate having first and second major surfaces;

arranging said first and second semiconductor substrates in stacked juxtaposition with each other to dispose said one major surface of said first semiconductor substrate in opposing registration with said other major surface of said second semiconductor substrate;

providing circuit function-performing areas on respective major surfaces of said first and second semiconductor substrates; and

interconnecting the circuit function-performing areas of said juxtaposed semiconductor substrates by forming contacts between at least some of said plurality of electrically conductive bonding pads on said second semiconductor substrate and the surface areas having the coating of electrically conductive material on said elevated portions of said first semiconductor substrate.

4. A method as set forth in claim 3, further including forming recesses in said first semiconductor substrate opening onto said one major surface thereof to define the boundaries of bridge areas of semiconductor material;

and

vertically flexing said plurality of elevated portions having said surface areas of electrically conductive material in the bridge areas of semiconductor material relative to said first semiconductor substrate sufficiently to accommodate registering contact with said at least some of said plurality of electrically conductive bonding pads on said second semiconductor substrate, thereby compensating for any non-level regions of said other major surface of said second semiconductor substrate.

5. A method as set forth in claim 3, wherein the application of an orientation dependent etch to said one major surface of said first semiconductor substrate forms a plurality of holes extending between said first and second major surfaces thereof;

and

applying an electrically conductive coating from one major surface of said first semiconductor substrate through each of said holes to the opposite other major surface of said first semiconductor substrate to provide electrical continuity between said first and second major surfaces of said first semiconductor substrate.

6. A method as set forth in claim 3, wherein at least said first semiconductor substrate is formed of (110) silicon material, and the application of an orientation dependent etch at the (110) plane thereof defines a plurality of vertically extending elevated portions from said one major surface of said first semiconductor substrate.

7. A method as set forth in claim 3, wherein

a plurality of elevated portions are formed upon one major surface of each of a plurality of semiconductor substrates, including said second seminconductor substrate, by applying an orientation dependent etch to said one major surface of each of said plurality of semiconductor substrates;

applying a coating of electrically conductive material to the surface area of each of said elevated portions formed on said one major surface of each of said plurality of semiconductor substrates;

forming a plurality of electrically conductive bonding pads on the other major surface of each of said plurality of semiconductor substrates, including said first semiconductor substrate;

arranging said plurality of semiconductor substrates in stacked juxtaposition with each other to dispose said one major surface of each of said semiconductor substrates in opposing registration with said other major surface of the semiconductor substrate adjacent thereto;

providing circuit function-performing areas on respective major surfaces of said semiconductor substrates; and

interconnecting the circuit function-performing areas of said stacked juxtaposed plurality of semiconductor substrates by forming contacts between at least some of said plurality of electrically conductive bonding pads on each of said semiconductor substrates and the surface areas having the coating of electrically conductive material on said elevated portions of the semiconductor substrate adjacent thereto.