Cross-point lightly-doped drain-source trench transistor and fabrication process therefor

• US 4,954,854 A
• Filed: 05/22/1989
• Issued: 09/04/1990
• Est. Priority Date: 05/22/1989
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lu, Nicky Chau-Chun, Dhong, Sang H., Hwang, Wei
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US07/355,232
• Time in Patent Office: 470 Days
• Field of Search: 357/23.4, 357/23.3, 357/23.6, 357/23.9, 357/55
• US Class Current: 257/332
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/39 the capacitor and the transistor being in a same trench
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

A structure and fabrication process for a self-aligned, lightly-doped drain/source n-channel field-effect transistor wherein a trench is formed in a well region in a wafer including an epitaxial layer on a substrate. A first, heavily doped drain region and bit line element is formed around the trench on the surface of the well, and a second, lightly-doped drain region is formed proximate to the first drain region and self-aligned to the trench sidewalls. A source region is located beneath the trench, which is filled with polysilicon, above which is gate and further polysilicon forming a transfer wordline. The well region at the trench sidewalls are doped to control the device threshold level, and the device is thereby also located at a wordline/bitline cross-point.

Claims

1. A self-aligned, slightly-doped drain/source field effect trench transistor device comprising:

a substrate having a lower portion of heavily doped n+ conductivity semiconductor material, the upper portion of said substrate being light doped n- conductivity epitaxial semiconductor material, said upper lightly doped portion being less conductive than said heavily doped lower portion,

a well region formed with p-type dopants disposed in said upper portion of said substrate.

at least one polysilicon filled trench extending from the surface of said well region and into said well region, said trench being electrically isolated from said well region by a layer of gate oxide insulation on the bottom and sidewalls of said trench between the well region and said polysilicon in said trench,

a source junction region located in said well region beneath the bottom surface of said trench,

a diffusion region forming a first drain junction region disposed in said well region, said first drain junction region being heavily doped with n++ type dopants, said first drain junction region being located on the surface of said well regional surrounding said trench,

a second lightly-doped drain junction region lightly doped with n+ type dopants in said well region proximate said first drain junction region and being self-aligned with the upper portion of said sidewalls of said trench, and

a polysilicon word line element disposed over said polysilicon filled trench.

2. A transistor device according to claim 1 wherein said well region forming said sidewalls of said trench are doped with p+ type dopants to control the n-channel threshold voltage of said transistor device.

3. A transistor device according to claim 2 wherein said diffusion region forming said first drain junction region also forms a bitline element for said transistor device, and wherein said bitline element and said polysilicon wordline element form a cross-point.