Integrated circuits

• US 4,954,865 A
• Filed: 05/05/1989
• Issued: 09/04/1990
• Est. Priority Date: 05/10/1988
• Status: Expired due to Term

• Current Assignee: STMicroelectronics NV
• Original Assignee: STC PLC (f/k/a Standard Telephones and Cables)
• Inventors: Rokos, George H. S.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): TRAN, MINH LOAN
• Application Number:
  US07/348,258
• Time in Patent Office: 487 Days
• Field of Search: 357/34, 357/43, 357/35, 357/59 E, 357/59 H, 437/31, 437/193
• US Class Current: 257/378
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: Y10S 438/98 Utilizing process equivalents or options

Abstract

An integrated circuit structure has a number of device areas each of which is configurable in a subsequent customizing process as a field effect transistor, a bipolar transistor or as a pair of those devices. Configuration of the structure is determined by correspondingly selective etching of a polysilicon layer disposed on the structure.

Claims

1. An integrated circuit structure adapted to provide a desired circuit function having a structure forming an element of any array of similar structures, the structure comprising a silicon semiconductor p^- -type substrate, an n^- -type epitaxial layer disposed on a major surface of the substrate, an n⁺ -type layer disposed between the epitaxial layer and the substrate and providing a burried layer below the epitaxial layer, an n⁺ -type sinker extending from the free surface of the epitaxial layer through that layer and providing electrical contact to the buried layer, a region of p^- -type material formed in the free surface of the epitaxial layer and spaced from said sinker, an insulating layer extending over the free surface of the epitaxial layer and having first and second openings in register with the p^- -type region and the sinker respectively, and a layer of polycrystalline silicon (polysilicon) applied to the surface of the structure and contacting the sinker via said openings, the structure being such that it is configurable by subsequent patterning of the polysilicon layer to define a polysilicon emitter body over the p^- -type region and a gate electrode on the oxide layer in a region between the emitter body and the sinker, said emitter body and gate electrode providing ion implementation masks for the fabrication of a polysilicon emitter transistor and a field effect transistor respectively.

2. An integrated circuit structure as claimed in claim 1, wherein the emitter body provides a mask for the ion implementation of a p⁺ -type dopant into said p^- -type region whereby to provide a bipolar base region.