Semiconductor wafer array with electrically conductive compliant material

• US 4,954,875 A
• Filed: 10/28/1987
• Issued: 09/04/1990
• Est. Priority Date: 07/17/1986
• Status: Expired due to Fees

• Current Assignee: Vertical Circuits Solutions, Inc.
• Original Assignee: LaserDynamics Inc.
• Inventors: Clements, Ken
• Primary Examiner(s): Mintel, William
• Application Number:
  US07/414,633
• Time in Patent Office: 1,042 Days
• Field of Search: 357/75, 357/81, 357/68, 357/55, 357/76
• US Class Current: 257/686
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/01019 Potassium [K]

Abstract

A semiconductor wafer array comprising a plurality of wafers of semiconductor material. Each of the wafers is provided with cone-shaped or pyramid-shaped vias. Inserted in each of the vias is a correspondingly shaped wad of electrically conductive compliant material for forming continuous vertical electrical connections between the wafers in the stack. The base of each wad makes connection to a bonding pad on the surface of a lower wafer as well as to the electrically conductive compliant material in the lower wafer.

Claims

1. A semiconductor wafer array comprising:

a plurality of wafers of semiconductors material which are stacked one on top of another, each of said plurality of wafers having

(a) a via which is in registration with a via in an adjacent wafer, said via in each of said plurality of wafers having a first end terminated by a first hole in a first surface of each of said wafers, a second end terminated by a second and relatively larger hole in a second and opposite surface of each of said wafers, and an inwardly directed wall surface in at least a portion of the wall between said first and said second ends;

(b) means for electrically insulating an exposed surface of said via in each of said plurality of wafers between said first and said second ends;

(c) an electrically conductive pad surrounding said first hole of said via in each of said plurality of wafers for making an electrical connection to electrical circuits located on said first surface of each of said plurality of wafers; and

(d) an electrically conductive compliant material which is located in said via in each of said plurality of wafers which, when not compressed, extends outwardly beyond respective planes of said first and said second holes of said via in each of said plurality of wafers; and

means for stacking a first one of said plurality of wafers on top of a second one of said plurality of wafers such that the compliant material which extends beyond said second hole of said via in said first one of said plurality of wafers will make an electrical contact with said electrically conductive pad surrounding said first hole of said via in said second one of said plurality of wafers and said compliant material which extends from said first hole of said via in said second one of said plurality of wafers.

2. An array according to claim 1 wherein said inwardly directed wall surface of said vias in each of said wafers restricts movement of said compliant material in said vias through said first hole when pressure is applied to said compliant material in the direction of said first hole.

3. An array according to claim 1 wherein said electrically conductive compliant material comprises a cone-shaped portion.

4. An array according to claim 3 wherein said electrically conductive compliant material comprises an elongated portion having substantially parallel side portions which extend from the apex of said cone-shaped portion.

5. An array according to claim 1 wherein said via comprises side walls having the shape of a truncated pyramid.

6. An array according to claim 5 wherein said via comprises an elongated portion having substantially parallel side walls which extend from the truncated end of said pyramid-shaped side walls.

7. An array according to claim 3 wherein said compliant material comprises a wad of wire.

8. An array according to claim 3 wherein said compliant material comprises a compliant electrically conductive elastomer.

9. An array according to claim 1 wherein said first surface of each wafer comprises a compliant electrically insulating material.

10. A semiconductor wafer array comprising:

a housing having a base plate and a top wall;

a plurality of wafers of semiconductive material which are stacked one on top of another between said base plate and said top wall, one of said wafers being located adjacent to said base plate, another of said wafers being located nearest to said top wall, each of said wafers having at least one via which is in registration with a via in another of said wafers, said via in each wafer having a first end terminated by a first hole in a first surface of said wafer, a second end terminated by a second hole in a second and opposite surface of said water, said second hole having a larger diameter than said first hole and an inwardly directed wall surface in at least a portion of the wall between said first and said second ends of said via;

means for electrically insulating the exposed surface of said via between said first and second ends thereof;

an electrically conductive pad surrounding said first hole in each wafer for making an electrical connection to electrical circuits located on said first surface of said wafer;

an electrically conductive compliant material which is located in said via in a wafer and, when not compressed, extends outwardly beyond the plane of said first and said second holes of said via in each wafer so as to make an electrical contact with the electrically conductive pad surrounding said hole and the compliant material in the via of an underlying wafer;

an electrically conductive feedthrough pin mounted in said base plate for making an electrical contact with said electrically compliant material in said via in said wafer located adjacent to said base plate; and

means located between said top wall and said wafer located adjacent to said top wall for applying pressure to said stack of wafers such that said compliant material in a wafer is compressed against the compliant material in a wafer adjacent thereto for forming an electrically conductive path between said adjacent wafers.

11. An array according to claim 10 wherein said pressure applying means comprises means for conducting heat from said stack of wafers to said top wall.

12. An array according to claim 11 wherein said heat conducting means for conducting heat from said stack of wafers to said top wall comprises a compliant member for compensating for thermal expansion and contraction of said stack of wafers.

13. An array according to claim 12 comprising means mounted in said top wall and extending outwardly therefrom for dissipating heat from said top wall.

14. An array according to claim 10 wherein each of said vias comprises side walls having the shape of a truncated pyramid.

15. An array according to claim 14 wherein each of said vias comprises an elongated portion having substantially parallel side walls which extend from a truncated end of said pyramid-shaped side walls.

16. An array according to claim 10 wherein said compliant material comprises a wad of wire having a bottom portion comprising an inclined surface extending inwardly from the bottom thereof toward the top thereof and an upper portion with generally parallel side wall portions.

17. An array according to claim 10 wherein said compliant material comprises a wad of electrically conductive elastomer material having a bottom portion comprising an inclined surface extending inwardly from the bottom thereof toward the top thereof and an upper portion with parallel side wall portions.

18. An array according to claim 16 wherein said bottom portion is cone-shaped.

19. An array according to claim 16 wherein said bottom portion is pyramid-shaped.

20. An array according to claim 17 wherein said bottom portion is cone-shaped.

21. An array according to claim 17 wherein said bottom portion is pyramid-shaped.