Processor-selection system

• US 4,954,945 A
• Filed: 03/05/1987
• Issued: 09/04/1990
• Est. Priority Date: 03/29/1986
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Inoue, Atsushi
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US07/022,087
• Time in Patent Office: 1,279 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 718/105
• CPC Class Codes: G06F 9/5066 Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs mappping at compile time, see G06F8/451

Abstract

A processor-selection system comprises a plurality of processors connected to each other via bus lines, and a processor-determining section for determining which processor can best execute a task requested by the processor. The respective processor comprises a task table for storing the types of processable tasks and processes performance levels, a flag register for storing a flag showing that the processor is now being occupied, and a comparator for delivering a process-enable signal to the processor-determining section, when a task-processing request made by another processor or processors is accepted, based on information contained in the task table and on the contents of the flag. The processor-determining section determines a suitable processor, in response to the process-enable signal, so that the requested task can be performed.

Claims

1. A processor-selection system comprising:

a plurality of processors connected to each other via bus lines, and capable of processing various tasks, said plurality of processors each having a predetermined performance level, generating a task-processing request together with the performance level to the other processors, and responsive to the other task-processing request from the other processors, to output a task-enable signal; and

processor determining means connected to the processors, for receiving the task-enable signal and determining which one of said processors is available for executing a requested task in accordance with the performance level, in response to the task-enable signal from at least one of said processors, and for outputting a level-changing signal for changing a requested task-processing performance level, in response to said processing-enable signal which is selectively output from said processor; and

said processing includes means for changing said task-processing performance level, in response to said level-changing signal and wherein said processor-determining means is comprised of means for determining whether or not the number of available processors is 1, 0, or more than 2, by way of a processing-enable signal from the processor, and for outputting a corresponding determining signal; and

said level-changing means has a function of lowering the processing performance level for the requested task, in response to the determining signal representing "0", and of raising the processing performance level for the requested task, in response to the determining signal representing more than 2; and

wherein said processors each comprise means for outputting information representing a type of a task to be processed and the performance level;

a task table for storing information representing various types of tasks and performance levels required for task processing;

flag-storing means for storing a flag showing whether or not the task is now being processed; and

means for determining, from the information of said task table and said flag, whether or not a task requested can be performed by another processor, and for outputting, when said task can be performed by another processor, a corresponding processing-enable signal to said processor-determining means;

2. The processor-selection system according to claim 1, wherein said level-changing means comprises storing means for storing a numerical value corresponding to the processing performance level for the requested task, and means for additively and subtractively performing an operation on said numerical value in said storing means, in response to the determining signal of said determining means.

3. The processor-selection system according to claim 1, wherein said determining means generates a first logical signal for lowering the task-processing performance level, in response to a first signal from all processors, indicating that the requested task processing is not possible, and a second logical signal for raising the task-processing performance level, in response to a second signal from at least two of said all processors, indicating that the requested task processing is possible.