Interleaved sensing system for FIFO and burst-mode memories

• US 4,954,987 A
• Filed: 07/17/1989
• Issued: 09/04/1990
• Est. Priority Date: 07/17/1989
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hoberman, Barry A., Auvinen, Stuart T.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/380,368
• Time in Patent Office: 414 Days
• Field of Search: 365/189.01, 365/189.02, 365/230.04, 365/189.05, 365/189.09, 365/230.02, 365/233, 365/230.08
• US Class Current: 365/189.02
• CPC Class Codes: G06F 5/00 Methods or arrangements for data conversion without changing the order or content of the data handled
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising

Abstract

An interleaved sensing system for decreasing the read access time in a sequential memory includes a sequential memory array formed of a plurality of memory cells for storing data. The memory cells are arranged in a plurality of odd columns and a plurality of even columns. Sensing means are provided for interleaving the stored data in the memory cells in the odd columns with the stored data in the memory cells in the even columns. An output buffer is coupled to the sensing means for generating data output representing alternately the stored data in the odd and even columns during alternate read cycles.

Claims

1. An interleaved sensing system for decreasing the read access time in a sequential memory, comprising in combination:

a sequential memory array formed of a plurality of memory cells for storing data, said memory cells being arranged in a plurality of odd columns and a plurality of even columns;

odd bit line means coupled to said plurality of odd columns;

even bit line means coupled to said plurality of even columns;

odd selecting means responsive to odd column select signals and coupled to said odd bit line means for accessing and transferring the stored data in selected ones of said memory cells in said odd columns to a pair of odd data lines;

even selecting means responsive to even column select signals and coupled to said even bit line means for accessing and transferring the stored data in selected ones of said memory cells in said even columns to a pair of odd data lines;

odd precharging means responsive to an odd precharging signal for precharging said pair of odd data lines prior to the transferring of the stored data in said odd columns to said pair of odd data lines;

even precharging means responsive to an even precharging signal for precharging said pair of even data lines prior to the transferring of the stored data in said even columns to said pair of even data lines;

odd sensing means coupled to said pair of odd data lines for sensing said stored data in said odd columns and for generating an odd output signal in response to an odd read signal;

even sensing means coupled to said pair of even data lines for sensing said stored data in said even columns and for generating an even output signal in response to an even read signal;

multiplexing means coupled to said odd and even sensing means for alternately supplying said odd output signal and said even output signal in a predetermined timing relationship; and

output means coupled to said multiplexing means for generating output data representing alternately said stored data in said odd and even columns in response to a read transfer signal.

2. An interleaved sensing system as claimed in claim 1, wherein said odd selecting means includes a plurality of first paired pass gate means, each of said first paired pass gate means being associated with a corresponding one of said plurality of odd columns.

3. An interleaved sensing system as claimed in claim 2, wherein each of said first paired pass gate means is formed of two N-channel MOS column select transistors.

4. An interleaved sensing system as claimed in claim 3, wherein said even selecting means includes a plurality of second paired pass gate means, each of said second paired pass gate means being associated with a corresponding one of said plurality of even columns.

5. An interleaved sensing system as claimed in claim 4, wherein each of said second paired pass gate means is formed of two N-channel MOS column select transistors.

6. An interleaved sensing system as claimed in claim 5, wherein said odd precharging means is comprised of a pair of N-channel MOS odd precharging transistors.

7. An interleaved sensing system as claimed in claim 6, wherein said even precharging means is comprised of a pair of N-channel MOS even precharging transistors.

8. An interleaved sensing system as claimed in claim 7, wherein said odd sensing means comprises an odd sense amplifier.

9. An interleaved sensing system as claimed in claim 8, wherein said even sensing means comprises an even sense amplifier.

10. An interleaved sensing system for decreasing the read access time in a sequential memory, comprising in combination:

a sequential memory array formed of a plurality of memory cells for storing data, said plurality of memory cells being arranged in a plurality of blocks of memory cells, said memory cells in each of said plurality of blocks being arranged in a plurality of odd columns and a plurality of even columns;

odd bit line means coupled to said plurality of odd columns in each of said plurality of blocks;

even bit line means coupled to said plurality of even columns in each of said plurality of blocks;

odd selecting means responsive to odd column select signals and coupled to said odd bit line means for accessing and transferring the stored data in selected ones of said memory cells in said odd columns to a pair of odd data lines;

even selecting means responsive to even column select signals and coupled to said even bit line means for accessing and transferring the stored data in selected ones of said memory cells in said even columns to a pair of odd data lines;

odd precharging means responsive to an odd precharging signal for precharging said pair of odd data lines prior to the transferring of the stored data in said odd columns to said pair of odd data lines;

even precharging means responsive to an even precharging signal for precharging said pair of even data lines prior to the transferring of the stored data in said even columns to said pair of even data lines;

odd sensing means coupled to said pair of odd data lines for sensing said stored data in said odd columns and for generating an odd output signal in response to an odd read signal;

even sensing means coupled to said pair of even data lines for sensing said stored data in said even columns and for generating an even output signal in response to an even read signal;

multiplexing means coupled to said odd and even sensing means for alternately supplying said odd output signal and said even output signal in a predetermined timing relationship; and

output means coupled to said multiplexing means for generating output data representing alternately said stored data in said odd and even columns in response to a read transfer signal.

11. An interleaved sensing system as claimed in claim 10, wherein said odd selecting means includes a plurality of first paired pass gate means, each of said first paired pass gate means being associated with a corresponding one of said plurality of odd columns.

12. An interleaved sensing system as claimed in claim 11, wherein each of said first paired pass gate means is formed of two N-channel MOS column select transistors.

13. An interleaved sensing system as claimed in claim 12, wherein said even selecting means includes a plurality of second paired pass gate means, each of said second paired pass gate means being associated with a corresponding one of said plurality of even columns.

14. An interleaved sensing system as claimed in claim 13, wherein each of said second paired pass gate means is formed of two N-channel MOS column select transistors.

15. An interleaved sensing system as claimed in claim 14, wherein said odd precharging means is comprised of a pair of N-channel MOS odd precharging transistors.

16. An interleaved sensing system as claimed in claim 15, wherein said even precharging means is comprised of a pair of N-channel MOS even precharging transistors.

17. An interleaved sensing system as claimed in claim 16, wherein said odd sensing means comprises an odd sense amplifier.

18. An interleaved sensing system as claimed in claim 17, wherein said even sensing means comprises an even sense amplifier.

19. An interleaved sensing system for decreasing the read access time in a sequential memory, comprising in combination:

a sequential memory array formed of a plurality of memory cells for storing data, said memory cells being arranged in a plurality of odd columns and a plurality of even columns;

sensing means for interleaving said stored data in said memory cells in said odd columns with said stored data in said memory cells in said even columns; and

output means coupled to said sensing means for generating output data representing alternately said stored data in said odd and even columns during alternate read cycles.

20. An interleaved sensing system as claimed in claim 19, further comprising selecting means and precharging means for transferring the stored data from corresponding bit lines to said sensing means at least one read cycle earlier than the present read cycle being accessed.